SURGE Silicon Valley

Silvaco continues on the great success of Silvaco Users Seminar at various Silvaco sites in 2019.

SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, explore smart application integration, and discover innovative techniques for advanced semiconductor design. The event includes eight demo stations, a catered lunch, and cool prizes and giveaways for attendees.

  • Executive keynotes
  • Technology Tracks: TCAD, EDA and Design IP
  • Roadmap presentations
  • Customer and partner presentations and success stories
  • Eight unique demo stations
  • Networking with industry experts

Silvaco Silicon Valley will be hosting SURGE on October 24, 2019. Please see the agenda below.

Venue:

  • Santa Clara Marriott
  • 2700 Mission College Boulevard
  • Santa Clara, CA 95054

Be sure to stay for a chance to win some great prizes!


Agenda

Time  
10:00AM Registration
11:00AM Welcome Address - Thomas Blaesi
11:05AM From Atoms to Systems - Babak Taheri Silvaco, Inc.
11:25AM MRAM - Low Energy Solutions for IoT - Tom Sparkman Spin Memory
11:45PM AI at the Edge: a New SoC Architecture - Gideon Intrater Adesto Technology
12:05PM Game Changing Efficient Memory for IoT and AI - Dr. Jack Guedj Numem
12:25PM Lunch

Time EDA Track
1:35PM Analog Custom Design and PDKs - Fred Sendig
2:00PM Using SmartSpice to Deliver Next-generation, Low Power Memory Systems - Cameron Fisher CEO, Mobile Semiconductor
2:25PM An Innovative Solution for Full Memory Yield Analysis - Dr. Firas Mohamed
2:50PM Coffee Break
3:20PM Accelerating Circuit Simulation Using Parasitic Reduction Tools - Tim Colton
3:45PM Standard Cell Library Tools and Services - Guilherme Schlinker
4:10PM SPICE Model Exploration Using Utmost IV - Sean Kelly

Time TCAD Track
1:35PM Background, Overview and Future of TCAD - Dr. Eric Guichard
2:00PM How TCAD can Optimize Power Devices - Dr. Derek Kimpton
2:25PM SPICE Modeling for Power Devices - Dr. Bogdan Tudor
2:50PM Coffee Break
3:20PM 3D NAND Memory Cell Simulation - Dr. Jin Cho
3:45PM Nanowire - From Atoms to Circuits - Udita Kapoor
4:10PM Stress Strain and Deformation - Sungwon Kong

Time IP Track
1:35PM Silvaco SIPware IP Overview - Jai Durgam
2:00PM SIPware Semiconductor IP for Samsung Foundry - Tim Dry
2:25PM Foundation IP and Services - Jens Michelsen
2:50PM Coffee Break
3:20PM Interface IP and Subsystems for IoT - Rajeev Huralikoppi
3:45PM IP Management with XENA - Jai Durgam
4:10PM Automotive IP Solutions - Thomas Blaesi

Time Closing
4:35PM Raffle

*Sessions and times are subject to change without notice.

Surge Highlights:

Thomas Blaesi
Welcome Presentation Thomas F. Blaesi
Vice President, Global Marketing, Silvaco, Inc.

Thomas F. Blaesi is Vice President of the global marketing group, which is chartered with defining, driving, and promoting Silvaco’s leadership in the TCAD, EDA and IP market. Key areas of responsibility include strategic planning, corporate marketing, product marketing, market research, brand management, corporate communications, and ecosystem alliance programs.

Thomas joined Silvaco in October 2017 with more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.

Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.

Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.

Babak Taheri
From Atoms to Systems Babak Taheri
CEO, Silvaco, Inc.

Babak Taheri is the CEO at Silvaco Inc., a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. Previously, he was the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.

While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).

Babak was the recipient of ”the perfect project award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college.

He also held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. He received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences, has over 20 published articles and holds 28 issued patents.

Tom Sparkman
MRAM - Low Energy Solutions for IoT Tom Sparkman
CEO, Spin Memory

Tom Sparkman has nearly 35 years of experience across medical, automotive, semiconductor and wireless technologies. His extensive leadership roles include CEO of Samplify Systems, a startup delivering mixed-signal semiconductor and ultrasound solutions, where he raised over $25 million in capital. Additional career highlights include 19 years at various executive positions at Maxim Integrated Products, General Manager and Senior Vice President of Worldwide Sales roles at Integrated Device Technology, and most recently, General Manager and Senior Vice President, Worldwide Sales at Spansion, Inc., prior to its merger with Cypress Semiconductor. Mr. Sparkman holds a Bachelor of Science in Electrical Engineering from the University of California at Berkeley.

Gideon Intrater
AI at the Edge: a New SoC Architecture Gideon Intrater
CTO, Adesto Technology

Gideon Intrater is Adesto’s Chief Technology Officer. He brings more than 30 years of experience in the semiconductor market to his role in the company. Gideon serves on the Advisory board of Think Silicon and was previously a member of the advisory board of Centipede Semi and Sansa Security (acquired by ARM in July 2015). Previously, Mr. Intrater was Vice President of Marketing at MIPS Technologies (until the company was sold in February 2013). Before joining MIPS, Mr. Intrater was Vice President of Architecture for Symwave, a privately-held supplier of high-performance analog/mixed signal semiconductor solutions for consumer devices. Prior to Symwave, Mr. Intrater held various management positions at MIPS Technologies and National Semiconductor Corporation. Mr. Intrater holds over 30 issued patents. He earned BSEE and MSEE degrees from the Technion, Israel Institute of Technology, and an MBA from San Jose State University.

Dr. Jack Guedj
Game Changing Efficient Memory for IoT and AI Dr. Jack Guedj
Co-Founder/CEO of Numem

Jack was President and CEO of Tensilica since 2008, where he transformed Tensilica into a rapidly growing company ascending to the #1 position in merchant DSP and ultimately leading to the Cadence acquisition in 2013 where he served as Corporate VP, Tensilica Products.

Prior to Tensilica Jack led the spin-out of Magnum from Cirrus Logic serving as founder, president and CEO. Jack led Magnum’s growth from ground zero to leadership in Multimedia SOCs for the Professional Video Broadcast, Consumer PVR TV/Camcorder/DVD Recorder and Set Top Box markets and the acquisition of the Consumer Products Group of LSI Corporation (C Cube). Prior to Cirrus, Jack was President of Tvia, Inc., leading that company’s successful IPO in August 2000. Jack holds an MBA from the UCLA Graduate School of Management. Jack attained a MSEE from Pierre & Marie Curie Engineering School of Paris, and a doctoral degree from the University of Pierre & Marie Curie.

Fred Sendig
Analog Custom Design and PDKs Fred Sendig
GM, Analog Custom Design Division, Silvaco, Inc.

Fred Sendig is the General Manager of Silvaco’s Analog Custom Design Division. He is responsible for driving the business and development efforts for custom design, physical realization, verification, PDK development and services. He brings nearly 35 years of experience in EDA and CAD to Silvaco having previously held positions of VP CAD and Methodology at Altera, Fellow/VP of R&D at Synopsys and R&D Fellow at Cadence.

Cameron Fisher
Using SmartSpice to Deliver Next-generation, Low Power Memory Systems Cameron Fisher
CEO, Mobile Semiconductor

Cameron Fisher has served as CEO of Mobile Semiconductor since co-founding the company in 2006. Prior to founding Mobile Semiconductor, Mr. Fisher served as the Director of the Low Power SRAM Design Group at Virage Logic Corporation in Seattle, Washington where he patented several low power design innovations.

With 25 years of experience in the semiconductor industry—18 of those years focused on embedded memory design—Mr. Fisher’s career experience includes starting a Seattle-based memory design center and leading advanced engineering teams from product conception to production.

Prior to co-founding Mobile Semiconductor, Mr. Fisher led engineering design of low power embedded SRAM solutions using 180nm through 65nm technologies for leading cellular manufacturers. His extensive experience in Integrated Device Manufacturer (IDM) semiconductor design organizations includes work with Intel, Boeing Semiconductors, Cascade Design Automation (later Duet Technologies), and Virage Logic Corporation.

Mr. Fisher earned his Master of Science in Electrical Engineering from Stanford University after receiving his Bachelor of Science in Engineering from Harvey Mudd College. In 2002, Mr. Fisher completed senior executive training with the renowned American Electronics Association (AeA)/Stanford Executive Institute.

Firas Mohamed
An Innovative Solution for Full Memory Yield Analysis Dr. Firas Mohamed
VP & GM, Machine Learning & Flow Optimization Division, Silvaco, Inc.

Dr Firas is General Manager of Silvaco France. He is Head of process variability and netlist reduction products line. Firas has over twenty-three years experience in the EDA industry.

Tim Colton
Accelerating Circuit Simulation Using Parasitic Reduction Tools Tim Colton
Applications Engineer, Silvaco, Inc.

Tim Colton Field Applications Engineer for backend products with over 30+ years in EDA working for various companies including Cadence, Mentor and Avanti.


Guilherme Schlinker
Standard Cell Library Tools and Services Guilherme Schlinker
Director of Layout Automation, Silvaco, Inc.

Guilherme Schlinker is Director of Layout Automation at Silvaco. He is responsible for Silvaco’s Layout Optimizer Product Line. Prior to joining Silvaco in 2018 he worked for 12 years at Nangate, where he developed EDA tools for layout automation and delivered standard cell library IP for multiple foundries and technology nodes. He joined Silvaco as part of the acquisition of Nangate and continues working with the former Nangate products. Mr. Schlinker holds a Computer Engineering degree from Universidade Federal do Rio Grande do Sul, Brazil.

Sean Kelly
SPICE Model Exploration Using Utmost IV Sean Kelly
Engineering Manager, Modeling, Silvaco, Inc.

Sean Kelly is the engineering manager for the Utmost IV device characterization and modeling tools. He has over 25 years of experience in process and device design, device characterization, spice modeling and EDA software development.

Eric Guichard
Background, Overview and Future of TCAD Dr. Eric Guichard
Vice President of the TCAD Division, Silvaco, Inc.

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations. Since joining Silvaco in 1995, he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations. Prior to joining Silvaco, Guichard was a senior SOI engineer specializing in transistor and circuit aging at LETI and Thomson Military and Space.

Dr. Guichard holds an MS in material science and a Ph.D. in semiconductor physics from Ecole Nationale Polytechnique de Grenoble, France.

Dr. Derek Kimpton
How TCAD can Optimize Power Devices Dr. Derek Kimpton
Principal Applications Engineer, Silvaco, Inc.

Dr. Derek Kimpton, Principal Applications Engineer at Silvaco, spent four years characterizing radiation effects on devices at Plessey Semiconductors in Lincoln, England. Whilst there he published the paper in Solid-State Electronics on a new and predictive total dose oxide charging model, that is the basis for the code implemented in Silvaco's latest TCAD Victory Device simulator.

Prior to his over 17 years at Silvaco, Dr. Kimpton received both a B.Sc. in Electronics and Ph.D. in GaInAs MOSFET fabrication from Kings College, London with an industrial year in the Optical Fiber division at GEC Hirst Research Center, in England. He also worked on the synthesis of silicon germanium (SiGe) by implantation of germanium as a Research Fellow at Middlesex University, England.

Dr Bogdan Tudor
SPICE Modeling for Power Devices Dr. Bogdan Tudor
Senior Manager, Device Characterization, Silvaco, Inc.

Bogdan Tudor is Head of Device Characterization for Silvaco, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software.

Dr Jin Cho
3D NAND Memory Cell Simulation Dr. Jin Cho
Applications Engineer, Silvaco, Inc.

Jin Cho is Principal Application Engineer at Silvaco, based in Santa Clara, USA. Prior to join Silvaco in 2018, he was with GLOBALFOUNDRIES/AMD for 15 years where he held the position of process/device manager of 14/10nm logic technology development and managed TCAD group for future device technology research. Jin holds a Ph. D. from Stanford University.

Udita Kapoor
Nanowire - From Atoms to Circuits Udita Kapoor
Field Applications Engineer, Silvaco, Inc.

Udita Kapoor joined Silvaco as a Field Applications Engineer within Silvaco’s TCAD division in 2019. She is based out of the Santa Clara office, California. Prior to Silvaco, Udita was at Rochester Institute of Technology, Rochester, New York, where she graduated with a Masters in Microelectronics. She is responsible for supporting TCAD for process simulation, training and supporting users in fabrication process simulations for various technologies. Udita has worked on simulation of classical and non-classical device simulations. She has worked with material characterization using atomistic modeling and device simulation for 2-D devices.

Sungwon Kong
Stress Strain and Deformation Sungwon Kong
Applications Engineer, Silvaco, Inc.

Sungwon Kong is a senior TCAD application engineer working in Silvaco US. He has been supporting TCAD applications for digital displays beginning at Silvaco Korea in 1996. He graduated from Inha University in electrical materials and device engineering and worked at Samsung Electronics at Gi-heung, Kung-gi-do before joining Silvaco.

Jai Durgam
Silvaco SIPware IP Overview Jai Durgam
VP & GM, IP Division, Silvaco, Inc.

Jai Durgam brings nearly 30 years of experience in the design, IP and EDA space. Most recently, Jai was the Vice President for Customer Design Enablement at Globalfoundries where he led all enablement, from PDKs & models to IP and design solutions for all GF nodes, including 22FDX and 14nm. Prior to that, Jai spent 11 years at Synopsys in multiple roles. From 2011-2016, he led world-wide Field Applications for Synopsys’ Solutions group for five years, supporting the complete IP portfolio from Synopsys. Jai was Sr. Director of Applications Consulting and Design Services for Synopsys India. Jai started his career at National Semiconductor Corp and has worked at Silicon Image and Scintera Networks. Jai has a Masters in Computer Engineering and Science from Oregon State University.

Tim Dry
SIPware Semiconductor IP for Samsung Foundry Tim Dry
Director of Marketing for Edge and End Point Segments,
Samsung Foundry

Tim has spent much of his career designing and marketing the technologies that we now consider foundation of the Edge and Endpoints.

In his current role, Tim leads the Automotive and IoT segment marketing at Samsung Foundry. This includes enabling value add IP and Samsung process node technologies such as 28FDSOI and FinFet geometries for Edge/End Point computing to customers. His focus includes eNVM, low power, AI, RF connectivity and security.

Prior to joining Samsung Foundry, Tim has worked at Global Foundries where he was Marketing Director for Industrial/IOT with an emphasis on AI and Embedded security. He also held various marketing and engineering roles at Renesas and Hitachi Semi focused on Smart Grid, MCUs, MPUs, connected devices (i.e. ZigBee, Power Line Carrier and more).

Tim has BSC EE from Liverpool John Moores University (UK) and MBA from San Jose State University.

Jens C. Michelsen
Foundation IP and Services Jens C. Michelsen
Business Director, Foundation IP, Silvaco, Inc.

Mr. Michelsen was Director of Physical Design at Vitesse’s Ethernet Products Division. Before joining Vitesse, he served as Physical Design Manager of Exbit Technology. Mr. Michelsen has more than 15 years’ industry experience within leading companies including Intel, Olicom and GN Nettest, in areas ranging from mathematical modeling to physical design. In recent years, physical design and design flow to tapeout have been his main focus. He holds several US patents in communications and IC design.

Rajeev Huralikoppi
Interface IP and Subsystems for IoT Rajeev Huralikoppi
Application Engineer, Silvaco, Inc.

Rajeev Huralikoppi is Application Engineer in Silvaco’s IP Division. He is responsible supporting the products of the I3C family. He brings over 25 years of experience in the Silicon Valley working for various companies like Synopsys, IPExtreme, Virtual Power Systems in the field of using IPs in ASIC and FPGA design.

Huralikoppi holds an MSEE in Electrical Engineering from University of Alabama in Huntsville in 1990.

Jai Durgam
IP Management with XENA Jai Durgam
VP & GM, IP Division, Silvaco, Inc., Silvaco, Inc.

Jai Durgam brings nearly 30 years of experience in the design, IP and EDA space. Most recently, Jai was the Vice President for Customer Design Enablement at Globalfoundries where he led all enablement, from PDKs & models to IP and design solutions for all GF nodes, including 22FDX and 14nm. Prior to that, Jai spent 11 years at Synopsys in multiple roles. From 2011-2016, he led world-wide Field Applications for Synopsys’ Solutions group for five years, supporting the complete IP portfolio from Synopsys. Jai was Sr. Director of Applications Consulting and Design Services for Synopsys India. Jai started his career at National Semiconductor Corp and has worked at Silicon Image and Scintera Networks. Jai has a Masters in Computer Engineering and Science from Oregon State University.

Thomas Blaesi
Automotive IP Solutions Thomas F. Blaesi
Vice President, Global Marketing, Silvaco, Inc.

Thomas F. Blaesi is Vice President of the global marketing group, which is chartered with defining, driving, and promoting Silvaco’s leadership in the TCAD, EDA and IP market. Key areas of responsibility include strategic planning, corporate marketing, product marketing, market research, brand management, corporate communications, and ecosystem alliance programs.

Thomas joined Silvaco in October 2017 with more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.

Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.

Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.