BSIM4 MOSFET Model Extraction

opt_ex19 : BSIM4 MOSFET Model Extraction

Requires: Utmost IV, SmartSpice, SmartView

Minimum Versions: Utmost IV 2.2.0.R, SmartSpice 4.30.0.R, SmartView 2.34.0.R

This example describes how to extract a standard BSIM4 model. To extract a model which is scalable with geometry, multiple different device sizes must be included. In this example, seven device geometries are included.

The project file opt_ex19.prj and the data file opt_ex19.uds for this example should be loaded into your database. When opened, the project will look as shown in opt_ex19_project.png .

The extraction and optimization sequence, which fully automates the extraction of this BSIM4 model, has fifteen sections. The objective of each section is to isolate a device characteristic and then to optimize only those model parameters which account for this device behavior.

Before starting the optimization sequence, the following device parameters are defined in the model library.

  • TOXE: Electrical oxide thickness
  • TNOM: Nominal room temperature

Section 1 : idvglin_large_rt

This section performs a preliminary extraction of the threshold voltage for the wide and long channel device, using the drain current versus gate voltage characteristic in the linear region and at room temperature. The extracted value is stored in the VTH0 model parameter, as shown in opt_ex19_01.png .

Section 2 : cgg

This section first performs a preliminary extraction of the oxide thickness based on Cgg versus gate voltage data. The extracted value is stored in the TOXE model parameter, as shown in opt_ex19_01.png .

Next, the following gate capacitance parameters are optimized using the same data:

  • TOXE Electrical oxide thickness
  • VTH0 Threshold voltage @Vb=0 for large L
  • VFB Flat band voltage @Vb=0
  • NDEP Channel doping concentration @Vb=0

After this step has been completed, the fit to measured data will be as shown in opt_ex19_02.png .

Section 3 : cgd

This section performs a preliminary extraction of the overlap capacitances using Cgd and Cgc versus gate voltage data. The extracted values are stored in the CGDO and CGSO model parameters, respectively, as shown in opt_ex19_03.png .

Section 4 : overlap

This section optimizes the overlap capacitance parameters using Cgd and Cgc versus gate voltage data. The following model parameters are optimized.

  • CGSO Non LDD region source-gate overlap capacitance per unit length
  • CGDO Non LDD region drain-gate overlap capacitance per unit length
  • CGSL Overlap capacitance between gate and LDD source region
  • CGDL Overlap capacitance between gate and LDD drain region
  • CKAPAS Gate-source overlap capacitance coefficient
  • CKAPAD Gate-drain overlap capacitance coefficient

After this step has been completed, the fit to measured data will be as shown in opt_ex19_04.png .

Section 5 : cgg

This section refines the parameters previously extracted in section #2 using Cgg data. The following model parameters are optimized.

  • TOXE Electrical oxide thickness
  • VTH0 Threshold voltage @Vb=0 for large L
  • VFB Flat band voltage @Vb=0
  • NDEP Channel doping concentration @Vb=0

After this step has been completed, the fit to measured data will be as shown in opt_ex19_05.png .

Section 6 : idvglin_large_rt

This section optimizes the I-V parameters for wide and long channel devices. The data in this section is the drain current versus gate voltage characteristic in the linear region and at room temperature. The following model parameters are extracted.

  • VTH0 Threshold voltage @Vb=0 for large L
  • U0 Mobility at nominal temperature
  • UA First-order mobility degradation coefficient
  • UB Second-order mobility degradation coefficient
  • K1 First-order body effect coefficient
  • K2 Second-order body effect coefficient
  • UC Body-effect of mobility degradation coefficient
  • NFACTOR Subthreshold swing factor
  • VOFF Offset voltage in the subthreshold region at large W and L
  • MINV Coefficient of moderate inversion

After this step has been completed, the fit to measured data will be as shown in opt_ex19_06.png .

Section 7 : cgg

This section optimizes a few extra gate capacitance parameters using Cgg data. The following model parameters are optimized.

  • VOFFCV CV parameter for weak to strong inversion
  • PHIN Non-uniform vertical doping effect parameter

After this step has been completed, the fit to measured data will be as shown in opt_ex19_07.png .

Section 8 : idvglin_warray_rt

The narrow width parameters are now extracted using data from devices with various channel widths and with a long channel value. The following model parameters are extracted.

  • WINT Width offset fitting parameter form I-V without bias
  • K3 Narrow width coefficient
  • W0 Narrow width parameter
  • K3B Body effect coefficient of K3
  • DWG Coefficient of Weff gate bias dependence
  • DWB Coefficient of Weff substrate bias dependence

After this step has been completed, the fit to measured data will be as shown in opt_ex19_08.png .

Section 9: idvglin_larray_rt

In this section, the parameters for short channel effects are optimized using devices of multiple lengths and wide channel value. The following model parameters are extracted.

  • LINT Length offset fitting parameter form I-V without bias
  • DVT0 First coefficient of short-channel effect on Vth
  • DVT1 Second coefficient of short-channel effect on Vth
  • LPE0 Lateral non-uniform doping coefficient
  • LPEB Non-uniform lateral doping effect on K1
  • RDSW Zero-bias LDD resistance per unit width (RDSMOD=0)
  • RDSWMIN LDD resistance per unit width at high Vgs and zero Vbs (RDSMOD=0)
  • DVT2 Body-bias coefficient of short-channel effect on Vth
  • PRWG Gate bias coefficient of RDSW
  • PRWB Body bias coefficient of RDSW

After this step has been completed, the fit to measured data will be as shown in opt_ex19_09.png .

Section 10 : idvglin_all_rt

This section refines the previously extracted I-V parameters using devices of multiple channel lengths and widths in the linear region and at room temperature ID-VG data.

After this step has been completed, the fit to measured data will be as shown in opt_ex19_10.png .

Section 11 : idvd_rt

The first 10 sections concentrated only on the linear regions drain current versus gate voltage for each of the different geometries. This section will use the saturation region drain current and conductances versus drain voltage data for all device geometries. The following parameters are optimized.

  • A0 Bulk charge effect coefficient for channel length
  • AGS Gate bias coefficient of the bulk
  • VSAT Saturation velocity at nominal temperature
  • PCLM Channel length modulation parameter
  • DELTA Effective Vds parameter
  • PDIBLC1 First output resistance DIBL effect correction parameter
  • PDIBLC2 Second output resistance DIBL effect correction parameter
  • DROUT L dependence coefficient of the DIBL correction parameter in Rout
  • ETA0 DIBL coefficient in subthreshold region
  • DSUB DIBL exponent coefficient in subthreshold region
  • PVAG Gate dependence of Early voltage
  • PSCBE1 First substrate current body-effect parameter
  • PSCBE2 Second substrate current body-effect parameter

After this step has been completed, the fit to measured data will be as shown in opt_ex19_11.png .

Section 12 : idvgsat_rt

This section extracts parameters responsible for the saturation drain current versus gate voltage characteristics with back bias. The following parameters are optimized.

  • KETA Body-bias coefficient of the bulk charge effect

After this step has been completed, the fit to measured data will be as shown in opt_ex19_12.png .

This completes the room temperature DC model, the following sections will deal with the temperature model.

Section 13: idvglin_large_t

This section extracts the model parameters for the large geometry drain current versus gate voltage linear temperature measurements. The following parameters are optimized.

  • KT1 Temperature coefficient for threshold voltage
  • KT2 Body-bias coefficient of the Vth temperature effect
  • UTE Mobility temperature exponent
  • UA1 Temperature coefficient for UA
  • UB1 Temperature coefficient for UB
  • UC1 Temperature coefficient for UC

After this step has been completed, the fit to measured data will be as shown in opt_ex19_13.png .

Section 14 : idvglin_t

Now we select all of the device geometries at temperature for the linear drain current versus gate voltage characteristics and optimize the following parameters.

  • KT1L Channel length sensitivity of temperature coefficient for threshold voltage
  • PRT Temperature coefficient for RDSW
  • KT1 Temperature coefficient for threshold voltage
  • KT2 Body-bias coefficient of the Vth temperature effect
  • UTE Mobility temperature exponent
  • UA1 Temperature coefficient for UA
  • UB1 Temperature coefficient for UB
  • UC1 Temperature coefficient for UC

After this step has been completed, the fit to measured data will be as shown in opt_ex19_14.png .

Section 15 : idvd_t

This section will extract the parameters for the saturation drain current versus drain voltage characteristics versus temperature. The parameters to be optimized are as follows.

  • AT Temperature coefficient for saturation velocity

After this step has been completed, the fit to measured data will be as shown in opt_ex19_15.png .

The sequence may be run multiple times in order to improve the fit of the model to the measured data as necessary. If needed, additional "bin" geometry dependence coefficients may be used to improve the fitting, similarly to the ones used in the BSIM3v3 optimization example (opt_ex09).

When complete, the model card can then be exported into an external model library file as shown in the output file opt_ex19.lib.