• Analog Custom Design & Analysis Examples

opt_ex14 : HiSIM_HV2 VDMOS Model Extraction

Requires: Utmost IV, SmartSpice, SmartView

Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.17.1.C, SmartView 2.28.2.R

This example demonstrates how to extract a standard HiSIM_HV2 model parameters for a single geometry Vdmos device. The datasets used are two drain current versus gate voltage characteristics at the low and the high drain voltages and one drain current versus the drain voltage characteristic. In addition, the capacitance data such as Cg_sdb, Cg_sb and Cgd are included.

The following process parameters are defined in the model library. The tox value is fixed during the optimization.

  • tox:Physical oxide thickness
  • nsubc:Substrate impurity concentration
  • nover:Impurity concentration of loverld at drain, and at source if cosym=1 and the value is declared

Also, the following model parameter values can be set to reasonable starting values. They are then optimized through the optimization sequence.

  • loverld:Overlap length at drain side, and at source if cosym=1
  • lovers:Overlap length at source side
  • ldrift1:Length of light doped drift region at drain, and at source if cosym=1
  • ldrift2:Length of heavily doped drift region at drain side, and at source if cosym=1

Note: The model flag cosym=0 is used.

Even though the Vdmos structure is different from the Ldmos, the drift region is only in the drain side similar to the Ldmos.

The project file opt_ex14.prj and the data file opt_ex14.uds for this example should be loaded into your database. When opened, the project will look as shown in opt_ex14_project.png .

The optimization sequence, which fully automates the extraction of HiSIM_HV2 model parameters, consists of seven sections. The section one is to get the initial estimate of the geometry correction terms. The section two extracts the threshold voltage region parameters. The third section is prepared to get the initial model parameters for the substrate current model. The section four aims to optimize the drift region resistance parameters at the low drain voltage. The bias dependency of the drift region resistance is optimized in the section five. And this completes the single geometry model parameters at the room temperature. The section six optimizes the temperature scaling model parameters to complete the HiSIM_HV2 DC model over the temperature change. The section seven is to get the gate capacitance characteristics.

Section 1 : Cg_sdb

The first section is to estimate the drift region overlap length parameters and the channel width correction parameters of HiSIM_HV2 using the Cg_sdb (Cgg) capacitance characteristics. The following model parameters are extracted.

  • loverld:Overlap length at drain side, and at source if cosym=1
  • xldld:Gate overlap length at drain side
  • xwd:Gate overlap width

After this section has been completed, the fit to measured data will be as shown in opt_ex14_01.png .

Section 2 : idvglin_cap_rtp

This section extracts the fundamental parameters for the Vdmos device. The data sets in this section are the drain current versus the gate voltage characteristic at the low drain voltage and the cg_sdb and cg_sb capacitance characteristics at the room temperature. The following model parameters are extracted.

  • nsubc:Substrate impurity concentration
  • vfbc:Flat band voltage
  • muecb0:Coulomb scattering
  • muecb1:Coulomb scattering
  • mueph0:Phonon scattering
  • mueph1:Phonon scattering
  • ndep:Depletion charge contribution on effective electric field
  • ninv:Inversion charge contribution on effective electric field
  • vfbover:Flat-band voltage in overlap region
  • nover:Impurity concentration of loverld at drain, and at source if cosym=1 and the value is declared
  • ldrift1:Length of light doped drift region at drain, and at source if cosym=1
  • ldrift2:Length of heavily doped drift region at drain side, and at source if cosym=1
  • rdrdjunc:Junction depth at channel/drift region for cordrift=1
  • rdrmue:Field dependent mobility in drift region for cordrift=1

After this section has been completed, the fit to measured data will be as shown in opt_ex14_02.png .

Section 3 : idvd_ref_rtp

The third section aims to obtain the initial values of the substrate current model and the channel length modulation parameters. The following model parameters are extracted.

  • bb:High field mobility degradation
  • sub1:Substrate current coefficient of magnitude
  • sub2:Substrate current coefficient of exponential term
  • svds:Substrate current coefficient of exponential term
  • svgs:Substrate current dependence on vgs
  • clm1:Hardness coefficient of channel/contact junction
  • clm2:Coefficient of qb contribution
  • clm3:Coefficient of qi contribution
  • sc2:Vds dependence of short-channel effect

After this section has been completed, the fit to measured data will be as shown in opt_ex14_03.png .

Section 4 : idvglin_cgs_ref_rtp

This section extracts several parameters of the drift region resistance model. The data in this section is the drain current versus the gate voltage characteristic at the low drain voltage and the cg_sb capacitance versus the gate voltage. The cg_sb capacitance is used to observe the effect of the drift region resistance parameters. The following model parameters are extracted.

  • rdrcx:Coefficient of current flow from xov for cordrift=1
  • rdrdl1:Effective ldrift of current in drift region for cordrift=1

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • nsubc
  • vfbc
  • muecb0
  • muecb1
  • mueph0
  • mueph1
  • ninv
  • ldrift1
  • ldrift2
  • rdrdjunc
  • rdrmue

After this section has been completed, the fit to measured data will be as shown in opt_ex14_04.png .

Section 5 : idvgall_idvd_ref_rtp

The previous four sections concentrated mostly on the drain current versus the gate voltage at the low drain voltage. The intention was to get the precise threshold model parameters. Also, the model parameters of the drift region resistance at the low drain voltage was extracted as the initial values for the succeeding optimization steps. This section will use the drain current versus the drain voltage data in addition to the drain current versus the gate voltage at the low and the high drain voltages to optimize the saturation region parameters and the drift resistance dependency on the drain and the gate voltages. The gate capacitances of cg_sdb and cg_sb are included to see the parameter effects. The following model parameters are extracted.

  • ninvd:Reduced resistance effect for small Vds
  • vmax:Saturation velocity
  • vover:Velocity overshoot effect
  • rdrcar:High field injection in drift region for cordrift=1
  • rdrqover:Inclusion of the overlap change in rdrift for cordrift=1
  • rdrvmax:Saturation velocity in drift region for cordrift=1
  • rdrbb:High field mobility in drift region
  • rth0:Thermal resistance
  • subld1:Substrate current induced in ldrift model
  • subld2:Substrate current induced in ldrift model

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • muecb0
  • muecb1
  • mueph0
  • mueph1
  • bb
  • ninv
  • ldrift1
  • ldrift2
  • rdrcx
  • rdrdl1
  • rdrdjunc
  • rdrmue
  • sub1
  • sub2
  • svds
  • svgs

After this section has been completed, the fit to measured data will be as shown in opt_ex14_05.png .

Section 6: idvgall_idvd_ref_tp

This section extracts the temperature model parameters using both the drain current versus the gate voltage and the drain current versus the drain voltage characteristics at three temperatures. The following model parameters are extracted.

  • bgtmp1:Temperature dependence of bandgap
  • bgtmp2:Temperature dependence of bandgap
  • muetmp:Temperature dependence of phonon scattering
  • vmaxt1:Temperature dependence of velocity
  • vmaxt2:Temperature dependence of velocity
  • vtmp:Temperature dependence of the saturation velocity
  • rdrmuetmp:Temperature dependence of resistance for cordrift=1
  • rdrvtmp:Temperature dependence of resistance for cordrift=1
  • rthtemp1:Temperature dependence of thermal resistance
  • rthtemp2:Temperature dependence of thermal resistance

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • bb
  • rdrbb

After this section has been completed, the fit to measured data will be as shown in opt_ex14_06.png .

Section 7 : gate_capacitance

This section is to finalize the gate capacitance characteristic fitting. The following model parameters are extracted.

  • xwdc:Gate overlap in width for capacitance calculation
  • cvdsover:Parameter for cgg for vds =! 0
  • cgso:Gate-to-source overlap capacitance
  • cgdo:Gate-to-drain overlap capacitance

The parameters used in the previous section are the following;

  • vfbover
  • loverld

After this section has been completed, the fit to measured data will be as shown in opt_ex14_07.png .

The sequence is prepared for the best fit. No repeated run would be necessary. When complete, the model card can be exported into an external model library file as shown in the output file opt_ex14.lib.

Note for reducing the run time.

Utmost IV is able to control the number of parallel runs of SmartSpice. The increase of number of smartspice shortens the run time for the multi-core machines. Edit -> Preferences -> Simulator

Additional Info:
Files
opt_ex14.lib
opt_ex14.uds
Graphics
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