HiSIM_HV2 LDMOS Model Extraction

opt_ex12 : HiSIM_HV2 LDMOS Model Extraction

Requires: Utmost IV, SmartSpice, SmartView

Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.17.1.C, SmartView 2.28.2.R

This example describes how to extract a standard HiSIM_HV2 model parameters. To extract a model which is scalable with geometry, multiple different device sizes must be included. In this example, three devices with the different channel width are used. And the device channel length is the drawn poly gate length which overlaps the intrinsic channel and the drift resistance regions. The following process parameters are defined in the model library. The values of ldrift1, ldrif2 and tox are fixed during the optimization.

  • tox:Physical oxide thickness
  • nsubc:Substrate impurity concentration
  • nover:Impurity concentration of loverld at drain, and at source if cosym=1 and the value is declared
  • loverld:Overlap length at drain side, and at source if cosym=1
  • lovers:Overlap length at source side
  • ldrift1:Length of light doped drift region at drain, and at source if cosym=1
  • ldrift2:Length of heavily doped drift region at drain side, and at source if cosym=1
  • xldld:Gate-overlap length at drain side

The project file opt_ex12.prj and the data file opt_ex12.uds for this example should be loaded into your database. When opened, the project will look as shown in opt_ex12_project.png .

The optimization sequence, which fully automates the extraction of HiSIM_HV2 model parameters, consists of nine sections. The section one and two extract the threshold voltage region model parameters of HiSIM_HV2. The third section is prepared to get the initial model parameters for the substrate current model. The section four aims to optimize the drift region resistance parameters and the low field mobility parameters at the small drain and the gate voltages. The bias dependency of the drift region resistance is optimized in the section five to fit the drain current versus the drain voltage characteristics. This completes the reference geometry model parameter extraction at the room temperature. The section six through the eight optimize the geometry and the temperature scaling model parameters to complete the scalable HiSIM_HV2 model over the temperature change. The section nine is to get the gate capacitance characteristics. The green and red curves of the plots show the target data and the simulations, respectively.

Section 1 : idvglin_cap_rtp

This section optimizes the parameters of the threshold voltage region for the ldmos reference geometry device. The data in this section is the drain current versus the gate voltage characteristics in the linear region and the cgg and cgs capacitance characteristics at the room temperature. The following model parameters are extracted.

  • nsubc:Substrate impurity concentration
  • vfbc:Flat band voltage
  • muecb0:Coulomb scattering
  • muecb1:Coulomb scattering
  • mueph0:Phonon scattering
  • mueph1:Phonon scattering
  • xldld:Gate-overlap length at drain side
  • loverld:Overlap length at drain side, and at source if COSYM=1
  • lovers:Overlap length at source side
  • nover:Impurity concentration of LOVERLD at drain, and at source if COSYM=1
  • vfbover:Flat-band voltage in overlap region
  • cgso:Gate-to-source overlap capacitance
  • cgdo:Gate-to-drain overlap capacitance

After this step has been completed, the fit to measured data will be as shown in opt_ex12_01.png .

Section 2 : idvglin_warray_rtp

In this section, the parameters for narrow width effect are optimized using the devices of multiple width values. The following model parameters are extracted.

  • nsubcw:Modification of substrate concentration for narrow width
  • wl2:Threshold voltage shift due to small size effect
  • wvth0:Threshold voltage shift
  • muephw:Width dependence of phonon mobility reduction

Also, the following model parameters used at the previous step are included in this section to ensure the entire fitting.

  • muecb0
  • muecb1
  • mueph0
  • mueph1

After this step has been completed, the fit to measured data will be as shown in opt_ex12_02.png .

Section 3 : idvglin_idvd_ref_rtp

The section aims for getting the initial values of the substrate current model and the channel length modulation parameters using the drain current versus the drain voltage at the lowest vgs voltage. The following model parameters are extracted.

  • ndep:Depletion charge contribution on effective-electric field
  • ninv:Inversion charge contribution on effecitve-electric field
  • bb:High-field-mobility degradation
  • sub1:Substrate current coefficient of magnitude
  • sub2:Substrate current coefficient of exponential term
  • svds:Substrate current coefficient of exponential term
  • svgs:Substrate current dependence on vgs
  • clm1:Hardness coefficient of channel/contact junction
  • clm2:Coefficient of qb contribution
  • clm3:Coefficient of qi contribution
  • sc2:Vds dependence of short-channel effect

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • muecb0
  • muecb1
  • mueph0
  • mueph1

After this step has been completed, the fit to measured data will be as shown in opt_ex12_03.png .

Section 4 : idvglin_idvd_cgs_ref_rtp

The previous three sections concentrated mostly on the drain current versus the gate voltage at the linear region. The intention was to get the precise threshold voltage model parameters which are suitable for the different geometry devices. This section extracts several model parameters of the drift region resistance and the mobility model parameters for the reference geometry device. The datasets in this section are the drain current versus the gate voltage characteristics in the linear region, the drain current versus the drain voltage at the low vgs voltages and the cgs gate capacitance versus the gate voltage. The cgs capacitance is used to observe the effect of the drift region resistance parameters. The following model parameters are extracted.

  • muesr0:Surface roughness scattering
  • muesr1:Surface roughness scattering
  • ninvd:Reduced resistance effect for small Vds
  • vmax:Saturation velocity
  • rdrdl1:Effective ldrift of current in drift region for cordrift=1
  • rdrcx:Coefficient of current flow from xov for cordrift=1
  • rdrmue:Field-dependent mobility in drift region for cordrift=1
  • rdrqover:Inclusion of the overlap change in rdrift for cordrift=1

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • muecb0
  • muecb1
  • mueph0
  • mueph1
  • ndep
  • ninv
  • bb

After this step has been completed, the fit to measured data will be as shown in opt_ex12_04.png .

Section 5 : idvgall_idvd_ref_rtp

The previous step etracted the several drift region resistance parameters as the initial values for the succeeding optimization steps. This section will use the drain current versus the drain voltage data for the reference geometry to optimize all parameters of the drift resistance model. This step completes the single geometry model at the nominal temperature. The following parameters are extracted.

  • vover:Velocity overshoot effect
  • rdrcar:High field injection in drift region for cordrift=1
  • rdrdjunc:Junction depth at channel/drift region for cordrift=1
  • rdrvmax:Saturation velocity in drift region for cordrift=1
  • rdrbb:High field mobility in drift region
  • rth0:Thermal resistance

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • nsubc
  • vfbc
  • meucb0
  • muecb1
  • mueph0
  • mueph1
  • muesr0
  • muesr1
  • ndep
  • ninv
  • ninvd
  • bb
  • vmax
  • rdrcx
  • rdrdl1
  • rdrqover
  • clm1
  • clm2
  • clm3
  • sub1
  • sub2
  • svds
  • svgs

After this step has been completed, the fit to measured data will be as shown in opt_ex12_05.png .

Section 6: idvgall_idvd_ref_tp

This section extracts the temperature model parameters using both the drain current versus the gate voltage characteristics in the linear and the saturation regions and the drain current versus the drain voltage for the reference geometry device at three temperatures. The following parameters are extracted.

  • bgtmp1:Temperature dependence of bandgap
  • bgtmp2:Temperature dependence of bandgap
  • muetmp:Temperature dependence of phonon scattering
  • vmaxt1:Temperature dependence of velocity
  • vmaxt2:Temperature dependence of velocity
  • vtmp:Temperature dependence of the saturation velocity
  • rdrmuetmp:Temperature dependence of resistance for cordrift=1
  • rdrvtmp:Temperature dependence of resistance for cordrift=1
  • rthtemp1:Temperature dependence of thermal resistance

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • vfbc
  • ndep
  • ninv
  • rdrmue
  • rdrvmax

After this step has been completed, the fit to measured data will be as shown in opt_ex12_06.png .

Section 7 : idvgall_idvd_w_rtp

The previous section completed the single geometry temperature model. All geometry devices at the room temperature are used to fit the geometry scaling parameters in this section. The following model parameters are extracted.

  • xwd:Gate-overlap width
  • muepwp:Width dependence of phonon mobility reduction
  • muesrw:Change of surface roughness related mobility
  • mueswp:Change of surface roughness related mobility
  • muephs:Mobility modification due to small size
  • ninvdw:Width dependence of high field mobility
  • ninvdwp:Width dependence of high field mobility
  • rdrvmaxw:Saturation velocity wgate dependence for cordrift=1
  • rdrvmaxwp:Saturation velocity wgate dependence for cordrift=1
  • rth0w:Width dependence of thermal resistance
  • rth0wp:Width dependence of thermal resistance

Also, the following model parameters used at the previous steps are included in this section to ensure the entire fitting.

  • vfbc
  • mueph0
  • mueph1
  • muesr0
  • muesr1
  • ninvd
  • bb
  • vmax
  • vover
  • rth0
  • muephw
  • wvth0
  • sub1
  • sub2
  • svds
  • svgs
  • rdrdl1
  • rdrcx
  • rdrdjunc
  • rdrmue
  • rdrqover
  • rdrvmax
  • rdrbb

After this step has been completed, the fit to measured data will be as shown in opt_ex12_07.png .

Section 8 : idvgall_idvd_w_tp

The section is to complete the dc characteristics for all geometry devices at all temperatures. The following model parameters are extracted.

  • ninvdt1:Temperature dependence of universal mobility model
  • ninvdt2:Temperature dependence of universal mobility model
  • rthtemp2:Temperature dependence of thermal resistance

The following model parameters used at the previous steps are included in this section.

  • bgtmp1
  • bgtmp2
  • muetmp
  • vtmp
  • vmaxt1
  • vmaxt2
  • rthtemp1
  • rdrmuetmp
  • rdrvtmp
  • mueph0
  • mueph1
  • muesr0
  • muesr1
  • ninvd
  • vmax
  • vover
  • rdrmue
  • rdrvmax
  • rth0

After this step has been completed, the fit to measured data will be as shown in opt_ex12_08.png .

Section 9 : gate_capacitance

This section is to finalize the gate capacitance characteristic fitting. The following model parameters are extracted.

  • xwdc:Gate overlap in width for capacitance calculation
  • cvdsover:Parameter for cgg for vds!=0

The parameters used in the previous section are the following;

  • cgdo
  • cgso
  • loverld

After this step has been completed, the fit to measured data will be as shown in opt_ex12_09.png .

The sequence is prepared for the best fit. No repeated run would be necessary. When complete, the model card can be exported into an external model library file as shown in opt_ex12.lib.

Note for reducing the run time.

Utmost IV is able to control the number of parallel runs of SmartSpice. The increase of number of SmartSpice executions shortens the run time for the multi-core machines. Edit -> Preferences -> Simulator .