Buffer delay/risetime optimized for Vdd

005_buffer_delay : Buffer delay/risetime optimized for Vdd

Requires: SmartSpice & Smartview

Minimum Versions: SMARTSPICE 3.16.12.R

The input deck contains a buffer circuit to be optimized for geometry (W/L) to get the best rise, fall and delay times over a sequence of 4 operating voltages of 2.5v, 3.0v, 4.0v and 4.5v supply.

The parametric_data results of the optimization at each supply voltage level is printed as a table in the out log window. The final plot shows for each voltage some of the iterations to fulfill the optimization conditions.