• Analog Custom Design & Analysis Examples

    Analog Custom Design & Analysis Examples

001_rc_reduction : RC Reduction simple example

Requires: SmartSpice & Smartview

Minimum Versions: SMARTSPICE 3.16.12.R

SmartSpice RC-reduction tool:

SMARTSPICE has a built-in RLC-reduction tool that can be used on input decks that contain RLC parasitic elements.

To invoke RLC-reduction tool SMARTSPICE needs to be launched with '-rclevel <level_number>' command line option, where <level_number> is described as follows:

  • rclevel=0 - RLC-reduction for subcircuits
  • rclevel=1 - RLC-reduction for subcircuits with post-filtering
  • rclevel=2 - RLC-reduction for subcircuits and top-level
  • rclevel=3 - RLC-reduction for subcircuits and top-level with post-filtering
  • rclevel=4 - RLC-reduction for expanded netlist
  • rclevel=5 - RLC-reduction for expanded netlist with post-filtering
  • rclevel=6 - RLC-reduction for DSPF annotated netlist
  • rclevel=7 - RLC-reduction for DSPF annotated netlist with post-filtering

Example:

smartspice -b -rclevel 0 ex.in -or- smartspice -b -rclevel 2 ex.in -or- smartspice -b -rclevel 4 ex.in etc.

Details can be found in the SmartSpice User Manual 1 Chapter 15

The input deck is a SPICE file containing the test bench of SPICE statements, options, and models required to run ths simulation.

Input Files
Graphics
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