Verilog-A simple Resistor Chain

004_verilog-a_res : Verilog-A simple Resistor Chain

Requires: SmartSpice & Smartview

Minimum Versions: SmartSpice 4.6.8.R

This example shows how to use multiple Verilog-A modules in a simulation and to reference parameters of the module from the input deck.

This input deck consists of an sinewave source into a chain of 3 verilog-A resistor modules in series and then terminated by a spice element resistor and capacitor in parallel to ground. Internal resistance of the verilog-A module res_1 , res_2 and res_3 is set by the YVLG instance parameter that matches the parameter used in the verilog-A module (parameter 'R').

The output waveform shows the signal after each stage and finally charging the RC load components.