Inverter-equivalent Design (4-Bit Carry Look Ahead Adder)

011_hierarchical : Inverter-equivalent Design (4-Bit Carry Look Ahead Adder)

Requires: SmartSpice & Smartview

Minimum Versions: SmartSpice 4.18.16.R and SmartView 2.32.5.R

This hierarchical design example demonstrates inverter-equivalent implementation of complex gates connected as a 4-Bit Carry Look Ahead (CLA) Adder circuit . The 4-Bit CLA Adder is implemented with dynamic logic using a Manchester Carry Chain (MCC) architecture.

One approach to designing complex digital circuits matches complex gate performance to a base inverter. The approach defines NMOS and PMOS transistor W/L ratios in complex gates according to those established in the base inverter. In some cases, such as those found in the MCC subcircuit, the base inverter-equivalent ratios must be scaled in complex ways to achieve the essential requirements.

In the schematics and circuits that follow, notice the use of global width (W) and length (L) parameters to define the base inverter sizes which get passed along and scaled appropriately in each of the subcircuits. Furthermore, it is important to note that changes (rise or fall) on input signals should occur during the precharge phase of the clock signal (when clock is low). Output signals are considered valid during the evaluate phase of the clock signal (when clock is high) and after the requisite proagation delay for the signal of interest.

Important SmartSpice features demonstrated in this example include the following:

  • Creating an optimized INVERTER circuit using 0.18u MOSFET models to achieve a desired performance objective.
  • Creating an optimized 2-Input NAND gate with W/L ratios sized to match the base inverter.
  • Creating an optimized 2-Input AND gate using the INVERTER and NAND2 subcircuits.
  • Creating optimized 2-Input XNOR and XOR gates with W/L ratios sized to match the base inverter (also uses the INVERTER subcircuit).
  • Creating an optimized 4-Bit MCC circuit designed to handle 0.5pF load per internal-carry output signal.
  • Creating a 4-Bit CLA Adder using the subcircuits identified above.
  • Creating individual input decks to verify performance of all subcircuits and the full 4-Bit CLA Adder.

The INVERTER schematic illustrates the W/L ratios for the desired target performance. The INVERTER test schematic illustrates the INVERTER input deckused to simulate the transfer function (.DC analysis) and manually measure where the input voltage equals the output voltage. The INVERTER simulation output demonstrates these concepts.

The 2-Input NAND schematic illustrates the W/L ratios for the desired target performance. The 2-Input NAND test schematic illustrates the 2-Input NAND input deckused to simulate the transient response (.TRANS analysis) and visually verify functionality. The 2-Input NAND simulation output demonstrates these concepts.

The 2-Input AND schematic illustrates the gate constructed from the INVERTER and the 2-Input NAND. The W/L ratios are inherited from these base gates to achieve the desired target performance. The 2-Input AND test schematic illustrates the 2-Input AND input deckused to simulate the transient response (.TRANS analysis) and visually verify functionality. The 2-Input AND simulation output demonstrates these concepts.

The 2-Input XNOR schematic and the 2-Input XOR schematic illustrate these gates constructed with the INVERTER and the W/L ratios sized to achieve the desired target performance. The 2-Input XNOR test schematic and the 2-Input XOR test schematic illustrate the 2-Input XNOR input deckand the 2-Input XOR input deckused to simulate the transient response (.TRANS analysis) and visually verify functionality for each gate. The 2-Input XNOR simulation output and the 2-Input XOR simulation output demonstrate these concepts.

The MCC schematic illustrates the W/L ratios for the desired target performance. The MCC test schematic illustrates the MCC input deckused to simulate the transient response (.TRANS analysis) and visually verify functionality for all input combinations. The MCC simulation output demonstrates these concepts.

The 4-Bit CLA Adder schematic illustrates the full module constructed using the base subcircuits outlined previously (AND, XNOR, XOR, MCC). The 4-Bit CLA Adder test schematic illustrates the 4-Bit CLA Adder input deckused to simulate the transient response (.TRANS analysis) and visually verify functionality for all input combinations. The 4-Bit CLA Adder simulation output demonstrates these concepts.