DC match analysis

001_dcmatch_sim : DC match analysis

Requires: SmartSpice & Smartview

Minimum Versions: SMARTSPICE 3.16.12.R

The .dcmatch analysis statement in SmartSpice can be used to vary device contributions to the total deviation of a dc circuits charateristics. In this example a simple OpAmp circuit is used with the following variations:

  • Global: NMOS U0 = 10% PMOS U0 = 8%
  • Local: NMOS - Vth0 PMOS - Vth0
  • Element: R - r = 10%

The input deck is a SPICE file containing a variation block definition.

To run the simulation, Source the deck and press the green run button. When the simulation completes, the results are shown in SmartSpice log Window.

This shows the first output section due to the variation block in the GUI window, and is the first of 5 such reported variations in the log output.