• Analog Custom Design & Analysis Examples

    Analog Custom Design & Analysis Examples

006_vec_signal_state : Check output vs expected signal states

Requires: SmartSpice & Smartview

Minimum Versions: SMARTSPICE 3.16.12.R

The .vec statement keyword "check_window" allows a user to perform steady and non-steady checks of the actual signal states against the expected states. In this example we use non-steady state checks.

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