003_dot_dout : Dout (Expected State of Digital Output Signal)
Requires: SmartSpice & Smartview
Minimum Versions: SMARTSPICE 3.16.12.R
The .dout statement compares simulation results (node voltage) with the expected digital state during the transient analysis and generates an output report.
The .DOUT statement is used to compare simulation results (node voltage) with the expected digital state during the transient analysis and generates an output report.
Example deck demonstrates how to use .DOUT statement.
Statements : .dout x1.2 vlo vhi (10n 1 20n 0 30n 1) .dout x2.2 vlo vhi (10n 1 20n 0 30n 1)
1. Run the simulation input deck “Dout.in” in SmartSpice.
2. After simulation SmartSpice prints the following table:
***** Output vector error report *****
output signal at node [x1.2]: verified with no error. output signal at node [x2.2]: **warning** : incorrect x logic state at node [x2.2] time = 2.000000e-008, low expected!
Total number of .dout comparision errors : 1
Details can be found in the SmartSpice User's manual Chapter 3.13
Dout.in
* test .DOUT statement V2 3 0 pulse(0 5 0 0.001n 0.001n 10n 20n) X1 3 0 sub1 C = 0.1p X2 3 0 sub1 C = 1p .tran 1ns 30ns .param vlo = 0.1 .param vhi = 3.3 .dout x1.2 vlo vhi (10n 1 20n 0 30n 1) .dout x2.2 vlo vhi (10n 1 20n 0 30n 1) .save all .subckt sub1 1 0 R 1 2 5K C 2 0 c=C .ends .option nomod nodeck .END