• Analog Custom Design & Analysis Examples

    Analog Custom Design & Analysis Examples

001_biaschk : Biascheck functionality

Requires: SmartSpice & Smartview

Minimum Versions: SMARTSPICE 3.16.12.R

A 13 stage ring Oscillator built with fictional BSIM4 models is used to show how you can setup the .BIASCHK functionality to monitor a differential potential across the MOS devices in the circuit to compare to a fixed value and report when this value is exceeded. The input deck has these 2 important seup lines:

  • .biaschk NMOS detailed condition = "ABS(V(nd)-V(ns))+ABS(V(ns)-V(nb))>1.8" terminal1=ngm terminal2=nsb limit=0.5 noise=0.01 name=m.xnandf.x7.mn1
  • .biaschk PMOS detailed condition="v(ng) < -(1+1)*.01" terminal1=ngp terminal2=nbp limit=0.5 noise=0.01 name=m.xnandf.x7.mp1

to setup checking of the NMOS and PMOS device conditions.

The output set of waveforms look like this plot and in the output log you can see the reported details where this condition has been exceeeded in amplitude and time during the transient simulation.

You can use this as a template to check devices in your particular circuit to make sure devices are exposed to right voltages and these conditions are not exceeded as this will affect the reliability of your circuit.

Input Files
Graphics
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