Faster Extraction of Designs with Large Amounts of Filling Metals

13 : Faster Extraction of Designs with Large Amounts of Filling Metals

Minimum Required Versions: Expert 4.10.37.R, Hipex 3.4.38.R

In the normal operation, Hipex-RC treats all dummy metal patterns as the normal conductor (the same way as interconnect wires). It causes a lot of nodes and parasitic devices, which increases the processing time not only for the parasitic extraction but also for the post-layout simulation.

To optimize the performance, those dummy metal patterns can be treated as a special shield layer. The dummy metal between two interconnect wires or between a interconnect wire and the substrate layer increases the total permittivity and causes higher parasitic capacitances.

So, different coefficient values may be applied for a couple of interconnect layers where dummy metal patterns are overlapping, such as the followings:

cpx Area metal2 substrate
1.04324e-005 * 1.59654
/outside_layers=metal1_dummy
;

cpx Fringe metal2 substrate
(3.25999e-005 * 1.59654),0.182479,1.11013
/outside_layers=metal1_dummy
/max_distance = 3
/max_width = 0
;

cpx Area metal2 substrate
1.04324e-005
;

cpx Fringe metal2 substrate
3.25999e-005,0.182479,1.11013
/max_distance = 3
/max_width = 0
;

Reduction of the number of nodes to be treated in the parasitic extraction makes the processing faster with fewer parasitic devices. It also reduces the processing time for the post-layout simulation effectively. The figure0 shows the results of the post-layout simulation with the following netlists:

tran1 : without parasitic RCs

tran2 : with parasitic RCs excluding dummy metals

tran3 : with parasitic RCs including dummy metals treated as normal interconnects

tran4 : with parasitic RCs including dummy metals treated as "outside_layers"

The results are almost same between the case where the dummy metals are treated as normal interconnects (tran3) and the case where they are treated as the "outside_layers" to increase the permittivity (tran4).

The actual operation steps are as follows:

1) Start Expert.

2) Go to File->Open , and load the project file h_13_1.eld.

3) Open the top cell hipex_example_13_1 in Open Cell(s) dialog. It includes a layout design of ring oscillator without dummy metal pattern ( figure1 ).

4) Select Verification->Extraction->Setup , Select Verification->Extraction->Setup to open the "Layout Parameter Extraction Setup" dialog. Press Load button, and choose hipex_example_13_1.lpe file to load required extraction settings.

Open "Technology" page, and make sure that a parasitic capacitance technology file without_dummy.cmd is specified.

5) Select Verification->Extraction->Hipex-net->Run to obtain a SPICE netlist not including parasitic devices.

6) Select Verification->Extraction->Hipex-RC->Run to obtain a SPICE netlist containing parasitic RC devices.

7) Select Verification->Node-Probing->Pick Node , and click the interconnect wire at the left bottom. The value of the extracted parasitic capacitance will be indicated ( figure2 ).

8) Go to File->Open , load another project file h_13_2.eld, and open the top cell hipex_example_13_2, which includes dummy metal patterns ( figure3 ).

9) Select Verification->Extraction->Hipex-net->Run , and Verification->Extraction->Hipex-RC->Run in the same way as 5) and 6). The processing time will be almost doubled than that of the previous processing, because of much more nodes and parasitic devices generated.

10) Select Verification->Node-Probing->Pick Node, and click the interconnect wire at the left bottom again. The value of the extracted parasitic capacitance will be greater than the previous one ( figure4 ).

11) Go to File->Open , load another project file h_13_3.eld , and open the top cell "hipex_example_13_3". The layout design is completely same as the previous one, but has some different settings for processing of dummy metal patterns.

12) Select Verification->Extraction->Setup , open "Technology" page, and make sure that a parasitic capacitance technology file with_dummy.cmd is specified.

13) Select Verification->Extraction->Hipex-net->Run , and Verification->Extraction->Hipex-RC->Run in the same way as 5) and 6). The processing time will be recovered to the same time as the first processing, because the number of parasitic RC devices are reduced by the setting of dummy metal patterns.

14) Select Verification->Node-Probing->Pick Node , and click the interconnect wire at the left bottom again. The value of the extracted parasitic capacitance will be almost same as the previous one ( figure5 ).