Current Starved VCO schematic

008_current_starved_VCO : Current Starved VCO schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R

Example 8 demonstrates a 5-Stage VCO design using a level=54 BSim4 SmartSpice model (see schematic.png ). The circuit can be used to generate clock signals for driving PLLs and other circuits. Using this design technique (current-starved), the current is controlled in each stage of the ring oscillator, achieving a wide frequency of operation. This design operates up to approximately 350MHz and the output is clamped to 1.4V.

The control file ( current_starved_VCO.ctr) shows the circuit to be run twice. The first time, a sine wave input at 4MHz is connected. Also, the: .PARAM VDD=2.2V GND=0.0V t=1.0us statement is defined so that any of these parameters may be changeable throughout the design by changing the value in the .PARAM statement. Since t=1.0us is defined, the time parameters in statements can be a function of t instead of using discrete times. In the example, the transient statement is set to run to time t, or to 1.0us.

After the first run, the input deck hits the .ALTER statement and then processes the statements that follow. In this example, the sinusoidal VIN input is replaced with a PWL piecewise linear voltage source defined in time-voltage (t, v) pairs. The values are defined in terms of t and VDD, respectively.

Upon completing the simulations, the wave forms are displayed (see waveforms.png ). Right clicking the plot and choosing to split the charts will make the charts look like the screenshot of the waveforms. By zooming in and using the period tool, the maximum operational frequency can be determined and displayed (see operational_frequency.png ).