RS Flip Flop Simulation

001_RSFF_sim : RS Flip Flop Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R

This RSFF simulation is designed hierarchically with the RSFF block sitting on the top level schematic. Descending one level down, the main flip-flop circuit is designed showing the 2 and 3-input NAND gates as the building blocks. Each NAND gate symbol may be further descended down to the cmos primitive schematic level.

The schematic (see top_level_schematic.png ) shows the RSFF block and the pinouts to the test bench.

The schematic RSFF.png contains the NAND gate circuitry that builds the device.

The control file RSFF_simulation.ctris a SPICE file containing the test bench of SPICE statements, options, and models required to run ths simulation.

The input deck RSFF_simulation.inis also a SPICE file and is generated by Gateway from the schematic. Gateway takes the control file and the netlist file to generate an input deck file. This input deck also includes information on specific voltages, currents, and vector data to be saved by the cross probes that are dropped on the schematic.

To run the simulation, press the run button. When the simulation completes, the resulting waveforms (see waveforms.png ) are shown in SmartView for postprocessing.