SURGE Silicon Valley

Silvaco announces the launch of a Silvaco Users Seminar at various Silvaco sites in 2017.

SURGE (Silvaco UseRs Global Event) is a premier and unique event brings together both the EDA as well as the IP community to discuss new technologies, smart integration for innovative applications and new techniques for realizing advanced designs.

  • Live demos of new features and capabilities
  • Unique variety of technical presentations
  • Roadmap presentations and exciting technology updates
  • Dynamic panel discussions and executive keynotes
  • Networking opportunities with industry experts

Silvaco US will be hosting SURGE on September 14, 2017.

Time:

  • September 14, 2017 12:30 - 9pm

Venue:

  • Santa Clara Convention Center
  • 5001 Great America Pkwy, Santa Clara, CA 95054


Stay and enjoy Networking (Happy Hour) hosted bar and hors d'oeuvres



Free prizes to all attendees.



Agenda

Time
12:30PM Registration
1:15PM Welcome Address - Mark Maurer
1:20PM Customer Appreciation Presentation - David L. Dutton
1:35PM Technology Updates From Silvaco CEO - David L. Dutton
Since Silvaco announced the entry of new CEO, David Dutton in 2014, he has continued to drive the company toward its next phase of innovation and growth. Where will Silvaco go from now on? He will introduce the strategy for Silvaco’s continued growth.
2:00PM GlobalFoundries Experience In Using Viso/Belledonne To Enable High Quality Foundry Deliverables - Venkat Ramasubramanian
How GlobalFoundries has adopted VISO/BELLEDONNE as part of PDK development & qualification flow and use the differentiated tool features to achieve high quality of foundry techfiles.
2:30PM A Review Of GaN-based Devices For Current And Future Electronics - Srabanti Chowdhury
In this talk, I will cover the two prominent geometries of GaN devices used in today's electronics- Lateral HEMT and Vertical FETs. The role that each of them will play in the upcoming power electronics market will be discussed shedding some light on their current performance and future possibilities.

Time Session 1 - Design and IP
3:00PM Silvaco Solutions For EDA Design - Brian Bradburn
Overview of Silvaco custom design flow with schematic capture (Gateway), layout editing (Expert), and physical verification (Guardian) to better equip your circuit designers.
3:20PM Simulation Of Highly Structured Designs in SmartSpice Pro/ SmartSpice Advanced Features For CPU Designers - Dr. Andrei Pashkovich
3:40PM Get A Head Start On Reliability Analysis In Your Design Cycle With InVar - Dr. Alex Samoylov
Get updated on best practices for ensuring robustness and ease-of-use in performing power, EM and IR drop analysis on various types of IC designs early in the design cycle using simple and minimalistic input data
3:55PM Innovative Solutions For SPICE SImulation Acceleration And Variation Management - Prashant Singh
Accelerate your design using the latest innovations in variations and reduction technologies to help improve your productivity.
4:10PM Coffee Break
4:20PM Analysis Of Parasitic RCs For Advanced Nodes - Colin Shaw
4:50PM What Makes SoC Design So Hard? - Jim Bruister
5:10PM I3C Enabling Next Generation IoT Devices - Warren Savage
I3C is a new MIPI™ interconnect standard that represents the next generation of technology to connect sensors to application processors at much higher speeds, lower power, and lower cost. Learn more about this important new standard and how Silvaco is leading the industry with a complete portfolio of I3C IP cores for your sensor and SoC devices.

Time Session 2 - TCAD And Modeling
3:00PM Enabling TCAD From mm To nm Scale Devices - Dr. Eric Guichard
Thyristor, IGBT, FDSOI, and FinFET are the main technologies behind automotive, IoT, and microprocessors respectively. We will review how we can simulate and optimize them using a common TCAD platform.
3:30PM Utmost IV And SPICE Modeling Challenges - Sean Kelly
SPICE modeling using Utmost IV is the link between process and design.eve Due to aggressive process scaling, device characterization becomes more and more demanding, while model complexity increases. We explore how Utmost IV helps to overcome these challenges. The Acquisition GUI Module provides a user-friendly way to control the measuring equipment and account for the parasitics introduced by test structures. The background communication with the instruments is controlled through a Javascript engine. This helps to conveniently debug and fix any customer issue. Model extraction through Utmost IV is fast and accurate. Compact models, macro-models, Verilog-A and TMI models are all supported. Using a very high speed SmartSpice interface, including parallelization, hundreds of curves per second are simulated. Model extraction is made easy through the convenient Optimization GUI Module and through the family of advanced local and global optimization algorithms. Direct extraction, manual and automatic optimization can be used. In each step of the flow an unlimited number of parameters can be optimized using any combination of targets. In conclusion, Utmost IV is a very powerful and user-friendly tool that empowers our customers to extract good models, critical for chip design.
4:10PM Coffee Break
4:20PM Use Examples Of Silvaco TCAD For Design And Analysis Of Lateral And Vertical GaN Devices On QST™ Substrates - Dr. Ozgur Aktas
5:00PM SPICE And Macro-Modeling - Designing With New Device Technologies - Bogdan Tudor
Using Silvaco modeling tools such as Utmost IV and TechModeler to create a methodology for macromodeling.

Time Session End
5:30PM Mechanisms Behind Accurate Parasitic RC Extraction - TCAD To SPICE - Dr. Eric Guichard
Learn how to delve behind the mysteries of parasitic extraction and solve your design challenges, Get introduced to the field solvers that enable you to be confident on your design whether it by deep-submicron, interconnect, touch panel, LCD, or further applications.
6:10PM Closing Remarks And Networking (Happy Hour)
*Tracks and times are subject to change without notice.

Surge Highlights:

Mark Maurer
Welcome Address Mark Maurer
Vice President, Business Development, Foundry & PDK, Silvaco

Mark Maurer is the Vice President of Business Development for Silvaco’s Foundry and PDK product areas. Since joining Silvaco in 2000, Mauer assumed responsibility for all defense business and most recently served as the company’s VP of Aerospace & Defense.


David L. Dutton
Technology Updates From Silvaco CEO David L. Dutton
CEO, Silvaco

Since Silvaco announced the entry of new CEO, David Dutton in 2014, he has continued to drive the company toward its next phase of innovation and growth. Where will Silvaco go from now on? He will introduce the strategy for Silvaco’s continued growth.


Venkat Ramasubramanian
GlobalFoundries Experience In Using Viso/Belledonne To Enable High Quality Foundry Deliverables Venkat Ramasubramanian
Director, Design Enablement at GlobalFoundries

Venkat Ramasubramanian is Director, Design Enablement at GlobalFoundries, responsible for design methodology & reference flow development. He has more than 17 years of experience in semiconductor industry spanning EDA and Foundry organizations.


Srabanti Chowdhury
A Review Of GaN-based Devices For Current And Future Electronics Srabanti Chowdhury
Professor, University of California Davis

Srabanti received her B. Tech in Radiophysics and Electronics from Institute of Radiophysics and Electronics, India and her M.S and PhD in Electrical Engineering from University of California, Santa Barbara.


Eric Guichard
Enabling TCAD From mm To nm Scale Devices Dr. Eric Guichard
Vice President of the TCAD Division, Silvaco

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations.


Brian Bradburn
Silvaco Solutions For EDA Design Brian Bradburn
Head of EDA, Front-End/Back-End, Silvaco

Brian Bradburn is Head of Silvaco's EDA product group, driving the design, development and vision of the front-end and back-end flow of products.


Dr Andrei Pashkovich
Simulation Of Highly Structured Designs In SmartSpice Pro/ SmartSpice Advanced Features For CPU Designers Dr. Andrei Pashkovich
Head of Simulation, Silvaco

Andrei Pashkovich is Head of Silvaco's Simulation products line, overseeing the group's R&D circuit simulation, numeric algorithms and semiconductor modeling activities.


Dr. Ozgur Aktas
Use Examples Of Silvaco TCAD For Design And Analysis Of Lateral And Vertical GaN Devices On QST™ Substrates Dr. Ozgur Aktas
Director of Device Technology

Dr. Aktas earned his Ph.D from University of Illinois at Urbana-Champaign. Dr. Aktas has an extensive publication record with 48 journal papers with more than 1500 citations, numerous conference presentations, and 2 issued US patents. During his career in the industry, Dr. Aktas made key contributions to the GaN power electronics programs at International Rectifier and Avogy, which includes development of test methods for understanding of reliability and performance issues of GaN HEMTs at International Rectificer and world’s first demonstration of avalanche in GaN p-n diodes in Avogy.


Dr Bogdan Tudor
SPICE And Macro-Modeling - Designing With New Device Technologies Dr. Bogdan Tudor
Senior Manager, Device Characterization, Silvaco

Bogdan Tudor is Head of Device Characterization for Silvaco, leading the UTMOST and Modeling Service teams. He has over 20 years of experience in model development and characterization software.


Alex Samoylov
Get A Head Start On Reliability Analysis In Your Design Cycle Dr. Alex Samoylov
Principal Applications Engineer, Silvaco

Alex Samoylov, has over 20 years of experience in the physical implementation area including power, timing, and reliability analysis for standard cell and transistor level designs.


Sean Kelly
Utmost IV and SPICE Modeling Challenges Sean Kelly
Engineering Manager, Modeling, Silvaco

Sean Kelly is the engineering manager for the Utmost IV device characterization and modeling tools. He has over 25 years experience in process and device design, device characterization, spice modeling and EDA software development.


  Colin Shaw
Analysis Of Parasitic RCs For Advanced Nodes Colin Shaw
Senior Applications Engineer, Silvaco

Colin is a Chartered Engineer with over 30years experience in the semiconductor industry. He has worked on Production/development of device process for both silicon and II-V compounds as well as device/circuit design covering test structure, SRAM, IGBT and SAW filters. He has characterised devices from low power through RF and Radiation, to high power devices to run in passenger trains. He is currently the company CMC and Si2 representative and active in the simulation of the latest devices both current and future structures plus helping customers to use Silvaco tools.


  Dr. Prashant Singh
Innovative Solutions For SPICE Simulation Acceleration And Variation Management Dr. Prashant Singh
Applications Engineer, Silvaco

Prashant Singh is a Senior Applications Engineer at Silvaco, and has over 20 years of experience in the design and simulation of high speed electronics and serial interfaces.


Jim Bruister
What Makes SoC Design So Hard Jim Bruister
President, SoC Solutions

Founder Jim Bruister has more than 35 years of experience in semiconductor design primarily focused on microprocessor, microcontroller, embedded software and hardware/software co-development and verification. His career has spanned the development of ASIC technology as well as EDA and the growth of design-reuse and silicon IP.


Warren Savage
I3C Enabling Next Generation IoT Devices Warren Savage
General Manager, IP, Silvaco

Warren Savage serves as the General Manager of Silvaco’s newly formed IP Division. He has spent his entire career in Silicon Valley with engineering and management roles in leading companies including Fairchild Semiconductor, Tandem Computers, Synopsys, and most recently with IPextreme.