Hipex Parasitic Capacitance Extraction (Hipex-C)

02 : Hipex Parasitic Capacitance Extraction (Hipex-C)

Minimum Required Versions: Expert 4.10.37.R, Hipex 3.4.38.R

This example demonstrates running Hipex Parasitic Capacitance Extraction on a layout in the Expert interactive layout environment.

1: Setting up Hipex-C with Expert

Start the Expert layout editor(either with the command expert or by clicking the expert icon). From the main menu bar at the top, click File->Open to pop up the Load Project menu, navigate to the directory into which the hipex_ex02.eld design database file was downloaded and Open it.This will call up the Open Cell(s) menus, and here double-click mux4, the top-level cell. By default this shows the hierarchical view of the design; you can see the full details ( figure1 ) by clicking View->Cell View->Flat. From the main Expert menu, click Verification->Extraction->Setup ; this pops up the Layout Parameter Extraction Setup panel (see Figure2 with Cell Explosion page shown). The pages within this panel are accessed using the menu on the left. The controls on these pages are used to load the required Hipex technology files and change any settings to customize the extraction. Refer to previous example (hipex_ex01) for overview of these controls.

To assure the anticipated behavior of the example, some controls need to be attended and values corrected if necessary.

In particular, for extraction a fully hierarchical netlist, click Set all->Hcell while visiting the fourth page ( Cell Explosion ).

Then, attend second page, Node Names , and make sure VDD is assigned as power node and VSS as ground node in "Global Node Names" section of this page.

Finally, choose the sixth page, Technology . For Derived layer generation , select Use external script and use the file browser to specify the hipex_ex02_lvs.dsf file previously downloaded. This file controls the generation of device recognition layers from the drawn/mask layers.

To specify settings for parasitic capacitance extraction, select Use external LISA script in the Parasitic capacitance technology section and use the file browser to specify the hipex_ex02_c.lisa file previously downloaded.

For settings to be in effect, click OK in the Layout Parameter Extraction Setup panel.

2: Hipex Parasitic Capacitance Extraction

First, the netlist extraction must be run, with Verification->Extraction->Hipex-Net->Run from the main Expert window. This step is necessary even if only the parasitics are required, because the full connectivity must first be extracted to identify all the nodes.

To perform parasitic capacitance extraction, invoke Verification->Extraction->Hipex-C->Run command from the main Expert window. When the parasitic capacitance extraction has completed, a window will popup, prompting to Close, Open Netlist or Show Detail (ie. show the run log). The Open Netlist option is worth noting; rather than simply showing a text netlist, it opens a Netlist Editor window (see Figure3 ), and shows both the text netlist (on the left) and a hierarchy display (on the right). These views are linked; clicking on a device in the hierarchy display will highlight the corresponding item in the text netlist. It is also linked to the layout, so clicking on the item in the hierarchy display will also jump to the relevant cell in the Expert layout editor. As with the plain netlist extraction, the parasitic extraction is actually done in different stages internally; the first stage is to create databases holding information about the parasitics, and the second stage is to generate netlists or parasitic files from the databases. So after creating the parasitic capacitance netlist, you can go into the Verification->Extraction->Netlister menu and create other types of netlists, including a flat netlist from the hierarchical databases: Verification->Extraction->Netlister->C Flat Spice Netlist (see Figure4 ).