Extraction of Analog (RF) Design

10 : Extraction of Analog (RF) Design

Minimum Required Versions: Expert 4.10.37.R, Hipex 3.4.38.R

The example circuit for Analog(RF) netlist extraction is the Low Noise Amlpifier (LNA) shown at figure1 . This single ended cascode design uses three 2Volt RF nmos transistors and three spiral inductors. Instructions for simulating the LNA and the use of the Gateway schematic editor and SmartSpiceRF simulation are given in the Radio Frequency Demo PDK. We will concentrate on the setup of the RF Layout design in EXPERT and the extraction of netlists with Hipex in this example. The layout design was done using the Netlist Driven Layout (NDL) flow from Gateway to Expert where an NDL netlist with device placement coordinates is generated in Gateway and imported into Expert as the initial placement of the devices showing flight lines where the devices need to be wired to each other.

1.0 Loading The Example Circuit into Expert

- Start Expert Layout Editor (with "expert &" on Linux or from the "Expert" desktop shortcut on Windows). Expert will start with a blank new session ( figure2 ).

- Configure EXPERT to access the Pcell library by selecting Library->Setup. The Library Setup window will appear ( figure3 ).Click Add, locate the file simucad_demo_pcells.eld (in this case it is under./pcells/), and click OK ( figure4 ).

- Load the LNA layout. For this, select File->Open and the Load Project dialog box will appear( figure5 ). Select the demo_sbcd.tcn as the technology file. If the Technology field is not accessible, click on the Options button in the lower right and select "use external technology for eld files" and also make sure that the option is set "Identify layers by name". The technology file has definitions which will be used for Netlist Extraction later.

Open the file LNA.eld . Press the Open button to open the selected file and the Cell Open dialog box will appear ( figure6 ). Open the LNA_completed cell to load the LNA layout ( figure7 ).

2.0 Configuring Layout Extraction

EXPERT offers built-in interface to provide communication to the Netlist Extraction (NLE) and Layout Parasitic Extraction (LPE) tools of Hipex family.

2.1. Configuring Netlist Extraction

Select View->Toolbar->LPE to view the LPE Toolbar ( figure8 ). The LPE Toolbar provides access to the extraction setup and main extraction functions. To access the configuration controls, select LPE icon or Verification->Extraction->Setup. In the left-hand panel, click on the Technology menu ( figure9 ). In order for Hipex-NET to generate the netlist from the design layout it needs to have extracted the devices by first deriving the additional device layers. In the Derived layer generation section select Use external script . Use the [...] browser button to find the demo_sbcd_lvs.dsf layer derivation file. It should be found in .../10/techfiles/hipex. In a course of running Netlist Extraction, EXPERT will actually use the *_lvs.dsf script to generate (in the background) derived layers on the LNA_completed cell in the LNA.eld library, and output LNA_completed$HPX.gds file for Hipex-NET to perform the device and parasitic extractions on. The generated GDSII file will contain the original layout's data plus the device recognition derived layers.

To configure generic devices for extraction, click on the Edit Devices button in Connectivity and Devices field to display the Device Setup screen ( figure10 ). Although the Generic devices are defined in the techfile the complex functions needed to calculate the equations based on the Auxiliary layers are defined in the LISA file, which must be configured within EXPERT. Hipex accesses these functions to evaluate any custom parameters needed to properly define a generic device. In the device, IND for example, custom parameters such as number of turns of the inductor coils or space between the turns are defined. The Auxiliary layers are created at the same time as all other derived layers.

2.2. Configuring Parasitic Extraction

The interlayer parasitic capacitances can be configured either using GUI or with use of LISA script. The latter way is chosen for presented example. In the Parasitic capacitance technology field of the LPE setup window ( figure11 ), select the Use LISA script file radio button and find the file demo_sbcd_dbc.lisa under .../10/techfiles/hipex.

Parasitic resistance parameters for this example are also defined with LISA script. In the Parasitic resistance technology field of the LPE setup window ( figure11 ), select the Use LISA script file radio button and find the file demo_sbcd_dbr.lisa under .../10/techfiles/hipex.

To provide further parasitic extraction tune-up, click Parasitic Extraction in the left panel of the LPE setup window. For presented example, the parasitic effects for some nets (power and ground) are not of particular interest; so they need to be eliminated from parasitic resistance and capacitance calculations: in the Ignored nets field, enter the names of the power and ground nets to be excluded from parasitic extraction. For example, type the net name VDD and click on the Add button ( figure12 ). Similarly, add the nets GND and VSS.

2.3. Configuring the Extraction Output

LPE can extract a variety of netlists. They can just be primary elements (*_hier.spice) or they can include parasitic elements, such as Rs and Cs (*_r_hier.spice, *_c_hier.spice, *_rc_hier.spice). These netlists can be created hierarchically or flat and can be separated, combined, or backannotated into another SPICE netlist. To see (and control) the Netlisting settings click on the Netlisting menu on the left-hand pane of the LPE Setup window. The Netlisting window will appear ( figure13 ). The file paths will obviously be different for your environment but the file names should be the same.

3.0 Running Netlist and Parasitic Extraction

To perform the basic netlist extraction, press the NET icon on the LPE toolbar or select Verification->Extraction->Hipex Net->Run from menu. The details of the run will appear ( figure14 ) in new window. EXPERT generates the LNA_opt.lisa (LPE Setup fields in Hipex format) , LNA_net_cmd.lisa (Tech file device and layer info in Hipex format), and LNA_completed$HPX.gds (LNA_completed cell with derived layers from EXPERT in gds format) files for Hipex-NET to use (to generate the netlists required). Select Verification->Extraction->Hipex Net->View Hierarchical Netlist to see the extracted netlist for our LNA_completed cell ( figure15 ). The EXPERT Netlist Editor gives a clear view of both the layout netlist, LNA_completed_hier.spice and it's hierarchical device audit including the devices' layout parameters.

To perform the Hipex-C extraction, press C icon on the LPE toolbar or select Verification->Extraction->Hipex-C->Run. Figure16 shows the details of the run. Select Verification->Extraction->Hipex C->View Hierarchical Netlist to see the extracted netlist with parasitic capacitors included ( figure17 ). The Netlist Editor clearly shows the parasitic capacitors in it's audit.

To perform the Hipex-R extraction, press R icon on the LPE toolbar or select Verification->Extraction->Hipex-R->Run. Figure18 shows the details of the run. Select Verification->Extraction->Hipex R->View Hierarchical Netlist to see the extracted netlist with parasitic resistors included ( figure19 ). The Netlist Editor clearly shows the parasitic resistors in it's audit.

To perform the parasitic RC extraction, press RC icon on the LPE toolbar or select Verification->Extraction->Hipex-RC->Run. Figure20 shows the details of the run. Select Verification->Extraction->Hipex RC->View Hierarchical Netlist to see the extracted netlist with both parasitic resistors and capacitors ( figure21 ).