Verilog Vending Machine Schematic Simulation

005_vending_machine : Verilog Vending Machine Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R

Example 5 is a schematic example of a finite state machine. The example models a vending machine that outputs a newspaper based on input combinations of coins. The top level schematic ( top_level.png ) shows the vend block on the test bench. Clicking on the block and descending shows the gate level view of the device ( gate_level.png ). A simulation of the circuit shows that when each coin is inserted, there is a 2-bit signal coin[1:0] that is send to the module. This signal is asserted at the next negative edge of the clock signal and stays high for one clock cycle. A high for coin[0] represents a nickel being deposited into the machine. A high for coin[1] represents a dime being deposited into the machine. When fifteen cents have been deposited based on any input combination, the newspaper signal goes high for one clock cycle and then is reset. The waveforms ( waveforms.png ) show output from the first run.

This was a gate-level representation of the device. Now, an RTL view of the vending machine can be substituted and simulated. To do this, delete the vend block on the top level schematic, and select the VendingMachine library from the library browser and instantiate the vend_rtl view. The vend.v RTL view shows the contents of the module. After resimulating the design with the RTL view, the output.png waveforms are identical.