JFET Sampling Gate Schematic

009_sampling_gate : JFET Sampling Gate Schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R

The schematic of the JFET sampling gate (see schematic.png ) shows the J1 JFET device used as a switch to sample the instantaneous amplitude of the input signal V1 several times during each cycle of the signal. J1 is switched on and off by the control voltage V2 applied to the gate terminal of the JFET. The addition of the capacitor C1 provides the abillity to hold the output voltage constant until the next sampling instant.

Simulating the example and then splitting the waveforms.png on separate charts shows the sample and hold functions

The control file for this example (see sampling_gate.ctr)shows a commented out .ST analysis that varies the pulse width of the sampling frequency. To enable the .ST, remove the asterisk character on the beginning of the line and save the control file. Then, on the schematic, switch to simulation mode (see simulation_mode.png ) and remove the input marker by clicking on the 'in' node. Re-simulating the design shows the results of the wider pulse width in the resulting waveforms (see ST_waveforms.png ).