Overview Process Simulation
3D 2D 1DDevice Simulation
3DStress Simulation Interactive Tools Virtual Wafer Fab TCAD Videos
Victory Device Device 3D Giga 3D MixedMode 3D Quantum 3D Luminous 3D TFT 3D LED 3D Magnetic 3D Thermal 3D2D
Mixed Signal, RF
Custom IC CAD
Downloads & Support
PDK Design Flows
Overview Available PDKs Foundry Partners Quality and Testing Maintainability PDK Development Services Documentation & Training Migration to Silvaco PDKs
Overview TCAD Services SPICE Modeling Parasitic Extraction PDK Development Cell Libraries and Blocks
003_abutment : Automatic Device Linking (Abutment)
Minimum Required Version: Expert 4.10.1.R
Device link improves the efficiency of layout design of CMOS logic circuits. By overlapping diffusion areas of MOSFET parameterized cells (PCells) that have a common net name, the PCells are automatically aligned and linked to each other.
It also recognizes whether an external connection exists from the connected pin and, if possible, can omit the diffusion contacts to minimize the spacing between the pair of gate regions.
In order to use the device link, a net name should be assigned to each pin on a MOSFET cell, as when it is supposed to be used within the schematic driven layout. Also, since the shapes of the diffusion area and contacts are controlled via PCell parameters, the MOSFET cell should be prepared as a PCell.
The actual operation steps are as follows:
Since some of the connected pins don't have any external connections,s the contact objects between gates will be deleted, and the spacing between the gates will be minimized as defined in advance (see 5_link_cmosn.png).