Partitioning and DRC for 3D systems & ICs

3D integration of ICs and systems is enhancing cost scaling of “More than Moore” technology and applications. However 3D integration of heterogeneous systems and ICs presents significant challenges to future designers. To that end we introduce two prototype design software for automatic 3D space partitioning of heterogeneous 3D IC designs, and 3D Design Rule Checking (3D DRC).

What attendees will learn:

  • Entry barrier: Difficulties facing 3D ICs and heterogeneous designers.
  • EDA Concept: Rationale behind the novel 3D space partitioning software and its integration with the 3D DRC tool
  • Design targets: Concept of weighted formulated design penalties
  • Design conflicts: Co-optimization of multi-physics criteria
  • Speed: High abstraction level for very fast simulations of complex orthogonal design criteria
  • Manufacturability: How the DRC violations in 3D space can be easily visualized and corrected
  • Case studies – 3D partitioning: How to obtain an optimal partitioning and placement of the blocks composing a 3D system in very short time
  • Case studies – 3D DRC: how to apply DRC checks in 3D space to feed subsequent full routing and final verification using traditional functional simulators

Presenter:

Stefano Pettazzi received his M.S. degree in Electrical and Electronics Engineering from University of Pavia, Italy. He has 15 years of experience in EDA and microelectronics companies. Since 2012 he has been working at Silvaco as Senior Applications Engineer supporting EDA software for both Back-End and Front-End design flows. Stefano is also in charge of several collaborative projects and responsible of the 3D IC software that Silvaco developed in the context of an EU-funded project.