Process Variation, Alignment and BEOL Effects on Circuit Level Performance

(Fully Integrated 3D TCAD, through SPICE Model and RC Parasitic Extraction to Circuit Simulation Flow)

 

Section 1: Introduction

As process nodes continue to shrink, the requirement for additional physics is gradually creeping into each stage of the design process. By way of illustration, TCAD simulations are becoming more atomistic in nature, SPICE models are becoming process-aware to take account of localized strain effects, and back or middle end of line (BEOL and MEOL) parasitics are moving from exclusively 2D rule based solutions to full 3D structure field solvers for numerous critical sections of the layout.

With this extra requirement for additional physics at all stages of the design flow in mind, Silvaco has created a single design interactive environment, to flow seamlessly from 3D Process and Device TCAD, all the way though to final SPICE circuit simulation including SPICE Model Parameter extraction from the TCAD simulations and 3D field solved back end of line resistance and capacitance parasitics. Designers can choose which part of the flow they wish to concentrate on, and the level of detail required to solve issues of interest. The versatility of the flow allows entire sections of the flow to be left out if not required. For example, if SPICE model cards are sufficiently accurate, the designer can omit the TCAD sections of the flow and concentrate on the back and middle end of line design optimization on circuit performance using the BEOL 3D structure builder and RC parasitic field solver sections.

This full 3D TCAD to SPICE Circuit Simulation flow is demonstrated allowing investigation of process, layout and alignment effects on final circuit level performance, using a high degree of automation within a universal iterative run time environment for every step in the sequence. Within each step in the flow, there is a huge range in the level of detail that can be accessed by the user, depending on which aspect or aspects of the design flow is of particular interest to the investigator. Aspects such as process parameters, stress effects, SPICE model fitting sequence, Back End Of Line (BEOL) parasitic resistance and capacitance optimization, to changes in circuit configuration can all be investigated in a single design environment with a single input command file. The tool flow sequence and user choices for each step are outlined in this article.

 

Section 2: TCAD to SPICE Simulation FinFET Flow Application Example

In order to illustrate the information flow, a ring oscillator circuit was chosen as an example, since such a circuit has obvious figures of merit for optimization, namely its oscillation frequency and power consumption per MHz. The whole of the simulation sequence below is executed from a single input command file that is run continuously from start to finish in either Silvaco’s DeckBuild or Virtual Wafer Fab (VWF) environments.

Section 2.1: Annotating the Input Layout File
Figure 1 shows the layout created as the input for this example, which consists of nine inverters connected in the usual ring configuration. Each inverter consists of two parallel connected n-FinFETs and two parallel connected p-FinFETs, each with fin widths of 10nm and drawn gate lengths of 20nm. The only labels in the original layout are VDD, VSS, IN, OUT and OUT2, which will be used for power supply connections and for monitoring output waveforms. All other required circuit node names will be generated by the tools in the flow.

Figure 1. The 9 stage ring oscillator layout created for this example.

 

As with any extraction sequence, the first task is to annotate the supplied layout file with additional layers and contacts for active device recognition, as well as providing these same required layers for the initial 3D process simulation of these same active devices. Additional required layers are created automatically by simple Boolean operation syntax in the layer map file in the usual way. This simply-created, ASCII text file also specifies layer connectivity, to automatically create the active SPICE Net list and a unique contact name for every terminal of every active device. The theory being, that if every terminal of every active device has a unique node identification in the active SPICE net list, then it is unlikely that any required SPICE circuit node is missing from the created net list. Even if certain nodes are electrically connected, a localized node for each FinFET terminal allows the calculation of parasitic resistance between each connected device using the 3D field solver described later in this article. The newly annotated layout is shown in Figure 2. Note the extra layers created to identify active device areas and their added labels uniquely identifying their SPICE circuit node names and 3D physical locations in the subsequent 3D TCAD and BEOL parasitic RC Field Solve simulations.

 

Figure 2. Annotated layout annotation for net list extraction showing extra created active device layers and SPICE node names.

 

Section 2.2: Creating the TCAD n- and p-FinFETs using 3D Process Simulation
The 3D Process simulation uses the newly created annotated layout above as input. The user selects relevant X-Y locations in the layout file as the areas to simulate the n- and p-FinFET devices. Any of the 18 n-FinFET and 18 p-FinFET devices in the ring oscillator layout can be selected for process simulation. In this example, devices from the middle inverter on the bottom row were selected for simulation. An important point here is that for most FinFET cell libraries, such as those from the Nangate company described later, the fins are in fixed X-Y locations, so the X-Y location of an individual FinFET for one cell, is likely the correct location in the layout for other cells. Sometimes there are two possible locations, for multi-patterning layouts, depending on whether the active devices are on the A or B variants of the same process layer.

In this example, we are going to create simple FinFET structures, since this example is more targeted towards CAD than TCAD. However, it is very important to point out, that the 3D process simulator used is a full functionality simulator, with very detailed process physics that could have been used at this stage of the flow if desired.

After selecting the area of the layout for FinFET simulation, this input file was set up such that the user inputs the fin_height, equivalent gate oxide thickness and source-drain diffusion time as input variables, and the complete process flow and device meshing is fully automated using just these user input variables. Figure 3 shows the automated creation of the p-FinFET, which includes SiGe source-drain stressors to increase the p-FinFET current drive to provide better drive current matching characteristics to the n-channel FinFETs. The stress calculations are performed during process simulation, and the resulting strain distribution passed to the device simulator described in the next section. The n-FinFETs are similar, but without the SiGe source-drain stressors.

Figure 3. P-Channel FinFET active device created from the same layout, showing SiGe source-drain stressors for mobility enhancement

 

Section 2.3: n- and p-FinFET Device Simulations
The purpose of the TCAD device simulations is to create a full set of 3D physics based I-V characteristics for use in the creation of an active device SPICE model that will be used in the final circuit simulation section. This automated SPICE model creation from 3D TCAD simulations, allows the investigation of process parameters and strain and layout effects on final circuit performance, providing a powerful tool for the circuit design optimization loop.

The I-V curve data set simulated in the 3D TCAD device simulator consisted of unsaturated and saturated Vt curves and a set of four IdVd curves for the n-and p-FET devices. Figure 4 shows these two curve sets for both n- and p-FinFET devices. For the Nangate cell designs described later, the FinFET intrinsic device capacitance data was also simulated and used for device model extraction, replacing the default capacitance values in the SPICE model.

Figures 4a and 4b: 3D FinFET device simulations for input into the automated SPICE model extraction routine.

As with the process simulations, the device physics included in these device simulations is up to the user. In this example, along with a standard model set, strain effects, gate tunneling and band to band tunneling physics were also included. Any available Silvaco model set or even user defined models could have been used if desired.

Section 2.4: SPICE Model Card Creation from the 3D TCAD Simulated I-V Curves
Once the 3D physics based TCAD simulations were completed, these TCAD I-V curves were used to create BSIM-CMG (Common Multi-Gate) FinFET SPICE Model cards for the n- and p-channel FinFETs. This CMG model is an actual FinFET specific full SPICE model approved by the Compact Modeling Council, as opposed to the usual Verilog model.

The exact routine for creating the model card could be customized if desired, using the UTMOST-IV GUI interface and a new script exported if necessary, but it was found that the script used in this flow worked very well for all process and layout variations tested, without any modification, so can be considered to be a sufficiently robust routine for these FinFETs to be effectively considered automatic (once defined). Following the automated routine, the SPICE model fit to the TCAD curves can be visually checked using the automatically plotted overlays. Curve fitting errors are also calculated and displayed to the user. Figures 5a and 5b show the SPICE model card fits to the TCAD data obtained without any additional input from the user of the input command file.

Figures 5a and 5b. Showing the automated SPICE model card fit to the TCAD data.

As can be observed from figures 5a and 5b, the automated SPICE model fit to the TCAD data is accurate enough to make it difficult to distinguish between the two sets of curves. An important point to make for Silvaco’s SPICE model parameter extraction tool, Utmost-IV, is that it uses the full SPICE simulator engine for fitting the curves, with no short cuts, thus ensuring that when the model is used during subsequent SPICE simulations, the active device characteristics obtained during the simulation will be an exact match to the extracted model card. Now that we have a good model card for the active devices, we can move on to the extraction of the full circuit back end of line (BEOL) parasitic resistance and capacitance extraction using the 3D structure field solver.

Section 2.5: Back End Of Line Resistance and Capacitance Parasitic Extraction
Silvaco’s back end of line 3D field solver tool combines a complete and powerful set of capabilities in a highly automated package. The tool combines passing layout dependent active device attributes, for active net list extraction, automated labelling of all active device contacts, BEOL 3D structure building, 3D field solving and automated RC parasitic back annotation onto the original extracted active SPICE net list, all from simple input ASCII format command file syntax.

The 3D BEOL structure used for the parasitic resistance and capacitance field solve step is shown in Figure 6. Once again, at this step there is a large number of options for the level of detail in creating the structure for the BEOL field solve steps, since the back end 3D structure builder, is the same as that used for the FinFET process simulations described above. In other words, the back end of line can be geometric in nature, with simple “delta CD” variances, or it can have a high level of process simulation detail, depending on which aspects of the circuit the user is trying to optimize or investigate.

Figure 6. The 3D BEOL ring oscillator structure used for parasitic field solve.

At the end of the field solve step, a complete SPICE net list is automatically created, including all the active and parasitic elements. This net list is in the correct SPICE syntax, such that the entire created net list is incorporated into the final SPICE simulation with a simple “.INCLUDE” statement in the SPICE simulation syntax section of the input command file.

Section 2.6: SPICE Circuit Simulation
Following the creation of the combined active and parasitic SPICE net list in the previous section, all that is required is to load this net list into a SPICE simulation, for circuit analysis. Normally, this would involve applying DC and transient test vector voltages as inputs, but the ring oscillator circuit used in this example requires no inputs. The only output is the ring oscillator frequency. Optimization parameters for the circuit could also include power consumption per MHz for example.

When extracting output waveforms and circuit performance parameters, there are two sources of such data when using Silvaco’s SmartSPICE circuit simulator. The SPICE engine itself has syntax for extracting circuit performance parameters, such as oscillation frequency and average power consumption, but the run time environment in which the input command file is running, also has its own built in extraction capability. Both can be, and are used, in this particular command file.

The advantage of using the run time interactive tool capability for extracting results in general, is that the extraction syntax is tool independent and can be used across different tools in a flow, as is the case in this example. Another advantage of using the internal parameter extraction of the run time environment, is that Silvaco’s Virtual Wafer Fab (VWF) can be utilized to run and control a large design of experiments (DOE) and then fit response surface models using its in built statistical capability, to relate the input variables to predicted outputs, even if that particular set of inputs was not specifically simulated during the DOE stage. This is usually referred to as a “Response Surface Model” or RSM.

Figure 7 shows the final SPICE circuit simulation of the ring oscillator circuit in the left plot, and the results of the automated frequency and average power consumption in the right hand plot. These output files are in the same format as the files generated using the 3D TCAD FinFET simulations, allowing the use of a single plotter for all curve types.

Figure 7. Ring oscillator output and extracted parameters of frequency and average power consumption.

 

Section 3: Application of this Flow to the Digital Cell Library from Nangate

In addition to the ring oscillator circuit described above, this flow was applied to four different digital cells from a Nangate digital library. In common with many such FinFET based technology libraries, the first step requires the creation of an additional mask layer which cannot be created from other existing mask layer combinations. This additional mask layer represents the silicon fins, on which the active devices are fabricated. This mask can be automatically generated, however, for all the logic cells, before proceeding with this flow and does not need to be created by hand for each cell.

The reason for the absence of this masking layer in FinFET based digital libraries is that individual active FinFETs are normally grouped together as being several identical devices in parallel. Leaving out each individual device, therefore allows active net list extractors to represent a number of individual devices in parallel as a single SPICE element, with the actual number of parallel fins being a parameter in the extracted SPICE model. This technique greatly reduces the individual element count required for SPICE simulation, thus proportionately speeding up any subsequent circuit analysis.

Once the additional “FINS” mask layer has been generated, selecting an area for active device TCAD simulations, and subsequent SPICE model parameter extraction is exactly the same as before, except that this time, as mentioned above, active device capacitance modeling was included in the TCAD device section and used in the active device SPICE model extraction, replacing the previously used default values. Interestingly, this had a significant effect on device switching speed, suggesting that the default values were significantly lower than those calculated by ac analysis on the TCAD devices.

For the 3D parasitic RC field solve structure, an additional level of detail was added to the simulation run, which now included the silicon fins and angled trench etch, together with a gate and S/D contact “local interconnect” layer, as shown in Figure 8. The “local interconnect” layer design rules for this particular process allow S/D contact local interconnect to bridge over active device gates without electrical contact, making the “local interconnect” more like a poorly conducting “metal 0” layer in functionality, rather than a true active device level local interconnect.

Figure 8. A clocked D-type Flip Flop structure example from the Nangate digital library.

Once the BEOL parasitics were added to the extracted active net list and incorporated into the SPICE simulator using the “.INCLUDE” statement, a logic test was simulated to check the clocked Flip Flop’s output response to every possible combination of inputs. The highest frequency input was applied to the clock pin, then one quarter of this frequency was applied to the “D” input, then one quarter of the “D input frequency was applied to “RN” input. Thus after a number of clock cycles, every possible logical input combination was tested on the logic circuit. The output from these truth table test vectors is shown in Figure 9.

Figure 9. The output “Q” from the clocked D-type Flip Flop, after application of full factorial test vector inputs to pins “CLK”, “D” and “RN”.

This input test vector can therefore be used to check for correct logic functionality after any input variations, such as deltaCD, layout design changes, process variations, etc.

 

Section 4: Running this Entire Flow in Silvaco’s Virtual Wafer Fab Environment.

Although the entire tool flow described above, from start to finish, can be a simple push button operation within the Silvaco’s DeckBuild run time environment, with each run using different input variables, the automation can be extended still further, using Silvaco’s Virtual Wafer Fab (VWF).

The Virtual Wafer Fab (VWF) tool allows any input file, using any combination of tools described above, to be turned into an automated design of experiments (DOE) where all variable names and output files are automatically managed. A virtual split lot tree can be built and run across multiple machines as shown in Figure 10, and the final results fitted to a response surface model, relating combinations of input variables to predicted outputs, as shown in Figure 11. Circuit and any other performance parameters can be extracted using the built-in extract syntax described above.

Figure 10. Creating a virtual spilt lot tree in Silvaco’s Virtual Wafer Fab environment, to analyze any parameter sensitivities to final circuit performance.

 

Figure 11. Creating a Response Surface Model (RSM) from the Design of Experiments (DOE) above showing circuit performance sensitivity to user specified variations or corner models.

The surface response plots can quickly give engineers actionable information and valuable insights as to which variables to target. For example, the surface response plots usually showed that maximum operational frequency had an inverse relationship to metal line width. This immediately indicates that the circuit is more parasitic capacitance dominated, rather than resistance dominated, since reducing metal line width increases parasitic resistance but has the opposite effect on parasitic capacitance. The circuit designer now has actionable information as to how to optimize the circuit for maximum operational frequency.

The power of this single command file approach, is that the effect of modification in any section of the flow (layout, process, material properties, etc.), can be observed directly on circuit level performance. This allows all engineers in each discipline to have a common target for their section of the design, namely that of final circuit performance parameters. Each designer can check in a modified section of the flow and measure circuit performance changes.

 

Section 5. Conclusion

In this article, we demonstrate the advantages of Silvaco’s policy of developing its core simulation tools in house from the ground up. This policy allows the core tools used in this article, namely:

(i) 3D Process and Device TCAD (Victory branded products)

(ii) SPICE model parameter extraction (Utmost IV)

(iii) Active net list extraction and 3D BEOL RC parasitics (Clever)

(iv) SPICE simulator (SmartSPICE) to all work seamlessly together in a single run time environment, without any necessity to manually save and re-load files from one simulator to the next.

A single input command file can be modified by a single or multiple users, depending on the engineer’s level of expertise in any of the tools. No matter what the specific tool expertise of the engineer, the full flow from TCAD to SPICE can be run from beginning to end by any engineer, to investigate the circuit level effects of changing any particular section of the tool flow.

For example, a TCAD process expert can modify the process flow section of the input command file, and immediately see the effects of such a modification on the final circuit performance, even if the engineer is totally unfamiliar with the SPICE syntax section of the command file. This provides individual empowerment to each engineer to fully understand the effects of any changes to any part of the tool flow without necessarily being an expert in all of the tools that are utilized in the design flow.

Taken one step further, if the tool flow is run in Silvaco’s virtual Wafer Fab (VWF) interactive tools, each engineer can perform a large design of experiments and create a response surface model for any section of the tool flow. This provides for any engineer a very fast appreciation as to the sensitivity of any changes in any section of the flow on the final circuit performance, thus solidifying the goals for each area of expertise to only one unified global circuit performance criteria perspective.