Simulation of Device Degradation Due to Bias Temperature Stress


Introduction Bias Temperature Instability (BTI) [1] ranks among the most serious reliability issues in present-day semiconductor devices. In pMOSFETs, for instance, it is observed when large negative biases are applied to the gate at elevated temperatures. These operation conditions cause a shift of the threshold voltage, resulting in an unwanted change of the device characteristics. With the continuous miniaturization of MOS devices, this phenomenon has become increasingly pronounced and has reached a level, at which it can even lead to device failure in the worst case.

In the past, BTI was associated with various different physical mechanisms, including the prominent reaction-diffusion model [2]. During the last couple of years however, experimental evidence has accumulated which confirms that charge trapping is responsible for the recoverable component of BTI. This trapping mechanism cannot be described by some kind of elastic tunneling, which is inherently temperature independent as opposed to BTI. However, hole trapping could be traced back to a temperature dependent process called multiphonon field-assisted tunneling (MPFAT). During such a process, the defect must be thermally excited first so that it can capture or emit a charge carrier followed by structural relaxation. The MPFAT process can explain the temperature and gate bias dependence of BTI and is the key component of the two-stage degradation model, implemented in the Silvaco TCAD tool Atlas. This model is a powerful tool for analyzing BTI on large-area devices, in which numerous defects are present. During the last couple of years however, a new measurement technique called time-dependent defect spectroscopy (TDDS) has provided insight into the detailed physics of the charge capture and emission processes of a single defect [3]. Using this method, the BTI trapping mechanism has been identified as a nonradiative multiphonon (NMP) process, which also forms the basis of the four-state NMP model. This new model can explain the single-defect measurements of TDDS but also the degradation data of large-area devices [4]. While the model was first developed for negative BTI in pMOSFETs, it has recently been shown to explain all four degradation modes, i.e. negative BTI and positive BTI in n-channel and p-channel MOS transistors [5].


The Four-State NMP Model

As mentioned before, the key component of this model are the NMP processes, illustrated in Figure 1. The energy of the neutral and the positive defect are shown as a function of the defect configuration q and have parabolic shapes in the harmonic approximation. During an NMP process, the defect must be first thermally excited up to the intersection point (IP) at the top of the NMP barrier. There, the defect can capture or emit a charge carrier since the defect energy is conserved while the charge is transferred. The NMP barrier is the cause for a marked temperature dependence, also observed in BTI experiments for example.

 

                 
Figure 1. Schematic illustration of an NMP process. Two defect energy curves are plotted for the case that the charge carrier to be trapped is either still located in the substrate or already captured in the defect. E1 (neutral, blue line) at q1 and E2 (positive, red line) at q2 denote the minima of the curves. During an NMP process, the defect has to thermally overcome the energy barrier over the intersection point. It is also mentioned that a change of the gate bias can lead to a upwards shift of the curve E1(q) and a lowering of the transition barrier (see dashed curve). This results in an increase of the hole capture rates, giving rise to a strong gate bias dependence, which is typical for BTI.

 

The above NMP processes are incorporated in the four-state NMP model, as depicted in the state diagram of Figure 2. The model is based on a set of four states, denoted as 1, 1’, 2, and 2’. The defect is assumed to be neutral in the states 1 and 1’ and positively charged in the states 2 and 2’. The states 1 and 2 are stable while the other states are metastable and marked by a prime (1’, 2’). The transitions 1 2’ and 1’ 2 represent NMP processes, the actual hole capture or emission events in the four-state NMP model. Since they involve metastable states, these NMP processes are always preceded or followed by defect deformations. The latter are independent of the local electric field and correspond to the transitions 11’ and 2 2’.

                 
Figure 2. State diagram of the multi-state model. The defects are stable in a neutral (1) and a positive (2) charge.state, where each of them has a metastable counterpart marked by a prime (1’,2’). The NMP transitions 1 2’ and 1’ 2 take place between different charge states. By contrast, the defect deformations 1 1’and 2 2’ occur between same charge states. It is stressed that the metastable states (1’,2’) are of particular importance as they strongly affect the gate-bias and temperature dependence of the overall transitions 1 2.

Even though several different transition pathways are possible in the state diagram of Figure 2, the whole charge capture or emission processes occur between the stable states 1 and 2 as two-step transitions. For instance, the whole hole capture process is usually described by a transition that starts from state 1, proceeds over state 2’, and ends up in state 2. During hole emission, the defect goes from state 2 to state 1 via either of metastable states 1’ or 2’. The different transition pathways can explain the behavior of the switching and the fixed oxide traps, respectively: The former are characterized by gate-bias dependent emission times and are described by a transition over the metastable state 1’ in the state diagram. By contrast, the fixed oxide traps take the pathway over the metastable state 2’ and have emission times that are insensitive to the gate bias.

The aforementioned four states describe the recoverable component of the BTI phenomenon and therefore build the core of the four-state NMP model. However, the experimental data also suggest the existence of a permanent (or slowly recovering) component. It has been linked to the generation of interface charges. However, the involved reactants have not been specified within this model. As such, the reaction can also be ascribed to the depassivation of Pb centers, which leaves behind a positively charged Si dangling bond. In contrast to the RD model, the degradation of the permanent component is not dominated by the dynamics of the hydrogen diffusion but by the kinetics of the interface reaction. This interface reaction is modeled by a double-well model with two stable states A and B (see Figure 3). The state A corresponds to a neutral interface defect and is energetically favorable compared to the positive interface defect in state B (in the absence of a large oxide field). However, an increase in the local electric field F lowers the energy barrier towards state B and thereby initiates a transition into state B.

                 
Figure 3. Schematic illustration of the interface reaction. If a bias is applied to the gate, the oxide field lowers the energy barrier, thereby initiating a transition from the state A to state B.

The recoverable and the permanent component are both caused by traps, whose properties vary from defect to defect in amorphous gate oxides, such as a-SiO2 and SiON. These variations lead to a wide range of transition times for the charge capture/emission processes and the interface reactions. A multitude of such traps allows for the long-lasting degradation and recovery curves seen in BTI experiments. It is emphasized that the degradation behavior of a device is therefore caused by the distributions of the defects properties.


Capture and Emission Time Plots

Since the four-state NMP model has to be consistent with the single-defect data of TDDS, the ATLAS implementation has first been evaluated against the data extracted from Ref. [3]. The simulated device was a simple planar p-channel MOS transistor with a plasma-nitrided oxide (EOT = 2.2 nm). As the defect parameters are assumed to be distributed in the four-state NMP model, they had to be calibrated against the experimental data. The calibration procedure was carried out for the data of the fixed and the switching oxide hole traps, depicted in Figure 4. It has been found that the simulation results agree well with the experimental capture and emission time constants for different gate biases and temperatures. This implies that the temperature dependence of the capture and emission time constants are well described by the thermal activation of the NMP processes. The model can also account for the different behavior of the fixed and the switching oxide traps (cf. Figure 4) – a fact that has only been achieved by the four-state NMP model so far. On the whole, the above evaluation against the TDDS data confirms that the four-state NMP model covers the essential physics of the hole capture and emission processes involved in the BTI degradation.

                 

Figure 4. Measured (symbols) and simulated (lines) capture and emission times of the fixed (top) and the switching (bottom) oxide trap. The good agreement with the experimental data show that the four-state NMP model captures the essential physics behind the charge capture/emission in BTI. Quite impressively, it can also give an explanation for both the fixed and the switching oxide traps.

 


Degradation Data

In this section the four-state NMP model is evaluated against the experimental long-term relaxation data, extracted from Ref. [4]. The measurements therein were carried out on of a p-channel MOS transistor with a 2.2 nm thick SiON gate oxide. For the following simulation study, the corresponding device structure was created using the Silvaco TCAD tool Victory Process (see Figure 5). It is mentioned that the generated mesh of the simulated device was highly refined in the oxide region between the substrate and the gate using the Silvaco TCAD tool DevEdit. The high resolution was required in order to account for the strong depth dependence of the charge trapping, which is inherent to every oxide trap model.

                 
Figure 5. The device structure used for the calibration of the fourstate
NMP model.

 

The device simulations included the last of several subsequent stress/relaxation cycles with the stress times of about 104 s and relaxation times of about 105. The selected dataset covers the three different stress biases (VG = −1.7/ − 2.7/ − 3.2 V) and two different temperatures (T = 125/170oC). This combination is suited to validate the four-state NMP model and in particular its oxide field and temperature dependence. For the given operation conditions, the relaxation curves were obtained by using transient simulations that cover the stress and the subsequent relaxation phase. In each of these simulations, the initial time step was set to a small value of 10−10 s in order to capture the fast degradation, which can even extend below the microsecond regime. At several times during the relaxation phase, structure files were stored using the SAVE statement. These files were later used to read in the trapped charges for calculation of the transfer characteristics and the extraction of the threshold voltages. This procedure was also used to determine the threshold voltage of the unstressed device, which is required for the calculation of the shift of threshold voltage.

Due to the computational costs, the numerous traps present in a large-area devices must be represented by a small number of stimulated traps. The parameters of the latter were assumed to follow a Gaussian distribution, however, the parameters of a single trap are still random values. Therefore, the number of representative traps was chosen sufficiently large so that their single contributions averaged out. In this study, the number of traps simulated was set to be 30 at each node.

The values of the trap parameters were specified using the syntax of the following TRAP statement:

1 TRAP material=SiO2 \
2 subcontact=Silicon gatecontact=Aluminum  \
 3 x.min=-0.05 x.max=+0.05 \
 4 y.min=-0.0015 y.max=-0.000 \
 5 nmp4.sto nmp4.samples=30 \
 6 density=6.379e+19 \
 7 sign=3.684e-13 sigp=3.684e-13 \
 8 nmp4.et1=3.760 nmp4.et1.sd=-0.257 \
 9 nmp4.s12s=2.431 nmp4.s12s.sd=-1.033 \
10 nmp4.r12s=1.960 nmp4.r12s.sd=0.394 \
11 nmp4.et2=5.263 nmp4.et2.sd=0.150 \
12 nmp4.s1s2=2.250 nmp4.s1s2.sd=1.001 \
13 nmp4.r1s2=1.175 nmp4.r1s2.sd=0.144 \
14 nmp4.nu=1e13 \
13 nmp4.epsT2s=0.319 nmp4.epsT2s.sd=-0.494 \
14 nmp4.eps2s2=0.209 nmp4.eps2s2.sd=-0.178 \
15 nmp4.eps1s1=3.000 nmp4.eps1s1.sd=0.000 \
16 nmp4.nit=9.494e+09 nmp4.nup=1e+13 \
17 nmp4.Ea=1.906 nmp4.Ea.sd=0.132 \
18 nmp4.Ed=0.277 nmp4.Ed.sd=0.000 \
19 nmp4.gamma=4.988e-08

The four-state NMP model was enabled by the flag nmp4.sto. The density of the oxide and interface traps were set by the parameter density and nmp4.nit, respectively. Furthermore, the oxide traps were placed within the insulator region that is defined by the material material=SiO2 and surrounded by the lines x.min, s.max, y.min, and s.max. The parameters subcontact and gatecontact specify the regions with which the oxide traps can exchange charge carriers via electron or hole trapping. The lines 6-15 of the above TRAP statement specify the parameters of the oxide traps while the parameters of the interface reaction are given in the lines 16-19. Most of these parameters are assumed to follow either a uniform or a Gaussian distribution and are therefore specified by their mean values and distribution widths. The latter has the ending .sd and must be set to a positive or negative value for a uniform or a normal distribution, respectively. Regarding the meaning of the parameter set, the reader is referred to the Atlas manual [7].

For the calibration of the model parameters, the Silvaco TCAD tool Virtual Wafer Fab (VWF) was chosen. It provides the Levenberg-Marquardt algorithm, which is a robust and established method to solve non-linear least square problems. As shown in Figure 6, the obtained simulation results agree well with the experimental data for all operation conditions. This demonstrates that the four-state NMP model explains the gate bias as well as the temperature dependence of the experimental data and is therefore suited to investigate the BTI degradation.

 

                 
Figure 6. The simulated (lines) and measured (symbols) relaxation data for four different operation conditions. The good match with the experimental data shows that the four-state NMP model is a good choice for investigating the BTI degradation. It is noted that the simulations do not only account for charge trapping with the substrate but also with the gate contact.


Summary

The Atlas package of Silvaco provides several degradation models, including the reaction-diffusion model and the two-stage model. This list of models has been extended now by the four-state NMP model, which was developed based on the physical insights from TDDS measurements and tested against the degradation data of several different device technologies. The TDDS simulations have demonstrated that the four-state NMP model covers the essential physics of the charge capture and emission process involved in BTI. Furthermore, the model has been validated by a fit to an experimental dataset including different gate biases and operation temperatures. Since the model accurately has reproduced the important characteristics of BTI, in particular the gate bias and the temperature dependence, it provides a good alternative to the existing degradation models implemented in the Silvaco TCAD tool Atlas.


References

  1. Schroder, D. et al., “Negative Bias Temperature Instability: Road to Cross in Deep Submicron Silicon Semiconductor Manufacturing”, J.Appl.Phys., vol. 94, no. 1, 1-8, (2003).
  2. Alam, M. et al., “A Comprehensive Model of pMOS NBTI Degradation”, Microelectronics Reliability, vol. 45, no. 1, 71-81, (2005).
  3. Grasser, T. et al., “The Time-Dependent Defect Spectroscopy (TDDS) for the Characterization of Bias Temperature Instability”, Proceedings of the International Reliability Physics Symposium (IRPS), 2A.2.1-2A.2.10, (2010).
  4. Rzepa, G. et al., “Physical Modeling of NBTI: From Individual Defects to Devices”, Proceedings of the 20th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 81-84, (2014).
  5. Rzepa, G. et al., “Complete Extraction of Defect Bands Responsible for Instabilities in n and pFinFETs”, 2016 Symposium on VLSI Technology Digest of Technical Papers, 208-209, (2016).
  6. Waltl, M. et al., “A Single-Trap Study of PBTI in SiON nMOS Transistors: Similarities and Differences to the NBTI/pMOS Case”, Proceedings of the International Reliability Physics Symposium (IRPS), XT.18.1-XT.18.5, (2014).
  7. Atlas User’s Manual, Device Simulation Software, SIlvaco, Inc., Santa Clara, CA 95054.