Using Victory Process to Create Realistic Structures for Capacitance Extraction in Clever


1. Introduction

Silvaco offers many alternatives for creating simple 3D structures, the optimum choice depending on what the user needs to simulate.  Many of the choices for creating simple 3D structures are for user convenience, so that just a single tool can both create the simple 3D structure and simulate the required physics. This gives the user an enhanced feeling of a tightly integrated product.

However, when realistic and curved 3D shapes are necessary, the complexity of the code required for their creation and subsequent meshing, necessitates that for efficiency sake, there is only one structure building interface. The idea being that there is only one complex 3D structure creator for realistic process simulation, and that this complex structure is then imported into the appropriate tool for device or back end simulations. To this end, when realistic process simulation is required to create a complex 3D structure, Victory Process will be used as the universal interface tool.

In this article, we demonstrate how to interface realistic 3D structures created using Victory Process, with the back end parasitic extraction tool, called Clever.  Clever uses a field solver operating on 3D structures to calculate both the parasitic resistance and capacitance of the interconnect lines within the structure.  If the 3D structure is “Manhattan” in nature (all features within the 3D structure are “square sided”), then Clever’s internal 3D builder is sufficient.  However, when realistic processing features are required, then the enhanced capability of Victory Process becomes necessary.


2. Complex Structure Creation Options within Victory Process

Within Victory Process, there are two methodologies for creating realistic structures, namely “Cell” mode and “Process” mode.

In technical terms, “Cell” mode utilizes an explicit structure mesh at all stages of structure creation, whereas “Process” mode uses a level set methodology, which separately tracks the location of moving boundaries during realistic etching and oxidation steps.  The advantage of the level set method (Process Mode) is greatly enhanced numerical stability when tracking moving interfaces during realistic etch and oxidation process steps.  The disadvantage of Process Mode is primarily simulation speed and structure file sizes.

In practical terms, use “Process” Mode if realistic and complex etching or oxidation is required to create the structure, but use “Cell” Mode for any other structure where geometric etching or oxidation steps will suffice.


3. An Example Using Victory Process in “Cell” Mode

Since both Process Mode and Cell Mode have realistic photolithography modules, and angled etches are covered under the geometric etching module, it is possible to make surprisingly realistic structures using the Cell mode 3D Process Simulator.  As an example, we shall create an SRAM cell, using the physics based photolithography simulator to create realistic photoresist development mask patterns, together with the geometrical angled etch engine to emulate the sloped sides of a dry etch machine.  The final structure is shown in Figure 1.

                 
Figure 1. An SRAM cell created using realistic photolithography and angle etched side walls, in Victory Process “Cell” Modeoperation.

The photolithography steps are carried out in 3 stages.  Firstly the optical properties of the mask aligner or stepper are defined, in terms of the wavelength of the optical source, the effective aperture of the focussing lens and the elevation of the focused image in reference to the top level of the photoresist.

Once the optical properties of the stepper have been defined, a physics based optical solver is invoked to calculate local photoresist exposure intensities. When the mask is exposed to the light source, an optical intensity pattern is created.  The spacial optical intensity pattern will approximately vary between full intensity exposure in the middle of large clear areas of the mask, and near zero intensity in large opaque areas of the mask.  The local spacial intensity is represented by a coefficient that varies between zero and unity to represent these two extremes of photoresist exposure intensity.  Near the edges of mask patterns, a contoured map of the spacial variance in intensity coefficient is formed as a result of diffraction and interference patterns. An example of a spacial intensity coefficient pattern is shown in Figure 2, in this case it is the spacial intensity pattern resulting from exposure to the gate mask, shown on the left.

                 

Figure 2. A gate mask and it’s resulting intensity coefficient map during photoresist exposure in the stepper.

 

After the photoresist exposure stage, the third stage is pattern development. In order to emulate variances in photoresist development conditions, e.g. over or under exposure time, bake times, development solution concentration etc., the user can choose the level of exposure which will define the final photoresist contour.  Figure 3 shows the final etch shape after development of the photoresist at a development threshold of a 40% (0.4) reduction relative to maximum exposure.

 

                 
Figure 3. Final photoresist mask shape after photolithography simulation.

 

Now the new mask shape after photolithography simulation has been defined, the angled etch of the polysilicon gate layer can proceed.  A typical etch angle of 87 degrees from horizontal was used to produce the final polysilicon gate layer shown in Figure 4.

                 
Figure 4. Polysilicon gate layer after photolithography simulation and an angled etch of 87 degrees.

 

Using the process steps described above, a realistic and complex cell can be created, as shown back in Figure 1.  Once we have the structure, it can be loaded back into Clever for interconnect resistance and capacitance field solving to obtain the resistance and capacitance parasitics, which are then back annotated onto the extracted active Spice netlist, also extracted by Clever.  The few and simple syntax lines required for the complete RC parasitic calculations and automated back annotation are shown in Figure 5.

                 
Figure 5. Syntax for RC Parasitic extraction and automatic back annotation.

To briefly review the extraction and back annotation syntax, the active netlist is extracted in the “init” statement, by loading of the layout and rule files (clex17_0.lay and clex17.lmp respectively) and the Victory Process created structure (clex17.str) is also loaded.  The two “Material” statement lines define some properties of the materials in the structure, which can be changed from their default values.  The “GateOx” material is assigned an un-physically low value of relative permittivity (0.01) in order to remove this gate capacitance from the net list, since this capacitance is already taken care of in the Spice model card of the active devices.   Finally, all parasitic RC calculations and automated back annotation onto the active Spice net list, are taken care of by the “Interconnect” statement, which requests 5% accuracy for both resistance and capacitance calculations.  The new netlist (active with parasitics) is saved into a Spice file called “clex17_1.net”.

In summary, therefore, the steps are as follows:

  1. Start Clever to create additional virtual masks required for process simulation
  2. Create the structure using Victory Process
  3. Load the structure back into Clever to perform interconnect parasitic resistance and capacitance calculations which are automatically back annotated onto the active Spice net list also extracted by Clever.


4. An Example Using Victory Process in “Process” Mode

 

The preceding example showed that complex and realistic looking structures can be constructed using just the geometric features of “Cell” mode operation in the Victory Process 3D simulator.  In cases where geometric operations are not sufficient for structure creation, such as where physical oxidation or reactive ion etching (RIE) are necessary, then the “Process Mode” operation of the Victory Process simulator has to be used.

The following example will show how to simulate a common processing issue, usually described as the “Micro-loading Effect” which is an annoying reality when etching small but varying feature sizes.  To summarize, the effect describes an apparent etch rate dependence on the feature size of the masked layer being etched.  Smaller apertures having a lower etch rate than slightly larger features.  For this and other reasons, it is common for the size of via holes for example, to be fixed for each layer.  In other words, the etch has only been optimized for this one size of hole for each layer.  The results are not guaranteed for any other size.   If you need a via for a higher current device, one simply has to use more of these fixed sized vias, in order to guarantee that the etch will yield for that layer.

Basically the procedure involves defining the type of etch machine, using the “TopographyModel” statement, and if it is a dry etch machine, as it is in this case, we then define the angular dependent properties of the plasma etch machine using the “Flux” definition statement.  In this example, the angular dependence of flux was described as having a Gaussian form. For a given angular distribution of flux, there can be different etch rates for each material exposed to the plasma, so the maximum vertical etch rates for each material are then defined on the EtchDepoProperties” statement.

Now the plasma etch machine has been fully described, all that remains to be done, is to expose our masked wafer to the virtual etch machine for a fixed period of time.  This is performed by the “Etch” statement.

To demonstrate the micro-loading effect, three trenches of differing sizes were defined by creating a hard etch mask and simple geometric etches.  The width of the “L” shaped trench patterns was 1um, 0.5um and 0.25um, as shown in Figure 6.

                 
Figure 6. The hard mask pattern before exposure to the etch machine.

After exposure to the etch machine for 4 minutes, effective width dependent etch rates were observed.  These trenches were then filled with aluminum to make observation of the trench depth dependence on trench width, easier to visualize.  The final structure is shown in Figure 7 with the surrounding material made transparent so that the internal shape of the etched trenches becomes apparent.

                 
Figure 7. 3D trenches modeled with a dry etch machine, clearly showing etch depth dependence on mask trench width.

To make the etch depth dependence on trench width even clearer, a 2D cutline through the structure shown in figure 7 is shown in figure 8.  In exactly the same way as in the “Cell” mode example, this structure can be loaded into Clever and the full capacitance matrix between the metal lines extracted.

                 
Figure 8. A 2D cut line through the structure shown in Figure 7, showing a clear etch depth dependence on trench width.

 

The details of the etch machine syntax will not be gone into here, as the structure above is now one of Silvaco’s standard Clever examples, and can be examined on our web page, or through the DeckBuild interface.


5. Conclusions

We have shown that any structure that can be created in Silvaco’s 3D Victory Process simulator can be loaded into Clever for capacitance and resistance extraction, either with or without active net list extraction.  This feature greatly adds to the versatility of this already versatile tool.