Vertical LOCOS Power Devices in Victory Process:
From 3D Process and Electrical Optimisation to High Speed, Full Chip Process Emulation

 

Introduction

There is a constant demand to lower the on-state resistance of devices, improving their energy efficiency as well as increasing their current handling capabilities whilst maintaining the desired breakdown voltage. However, a trade-off relationship exists between the on-state resistance and breakdown voltage. This is referred to as the silicon limit [1]. Attempts have been made to break the silicon limit. One such method proposed by several authors is the Vertical LOCOS MOS (VLOCOS) [2,3].

Such structures are relatively easy to simulate in 2D. However, the layout designs are inherently 3D [4]. Therefore it is critical that accurate and robust 3D simulations are undertaken to understand and fully optimize the electrical characteristics.

In this Simulation Standard article, a rigorous investigation is made into the effect that various different 3D corner designs have on device breakdown performance. The simulations are executed using Victory Process (VP), Silvaco’s fully three dimensional process simulation tool with 3D physical oxidation.

Firstly a simple introduction is given via means of a 2D structure. Large matrix simulations are then run on the 2D structure using Virtual Wafer Fab (VWF) to optimize the device.

The same matrix simulations are then run on 6 different 3D corner designs. One of the biggest challenges for this type of simulation is the oxidation of inherently complex 3D geometry. The investigation demonstrates VP’s ability to robustly handle the physical oxidation of complex 3D geometries. Discussion is also given to the physical operation of the structures considered.

Once device optimization is achieved and the layout generated, it is useful for the designer to be able visualize the full chip layout. VP can be run in Cell Mode, this mode is optimized for large areas with a highly efficient meshing algorithm and geometric process steps to emulate physical steps. All of these factors mean that a full chip geometric emulation flow can be simulated in a few tens of seconds. The last part of this article looks at one such example.

 

2D Device Cell Design

A simple 2D half-cell of a VLOCOS structure is shown in Figure 1. Typically [4] the device is formed by etching a deep trench into an N- substrate. The trench is then lined with a thermal oxide and refilled with polysilicon to form the gate. Subsequent P-, P+ and N+ implantations are made into the surface to form the P-Base channel region and the P+/N+ Source contacts.

 

Figure 1. Simple 2D VLOCOS structure for reference simulations.


The lower portion of the trench a thick oxide is formed. This thick oxide combined with the P-Base / N-Drift junction serves to deplete the N- Drift region when the device is blocking in a similar manner to a RESURF [5] or Super-Junction [6] type structures.

In the current investigation we are only concerned with the breakdown voltage, as such; the P+ and N+ source implants are not included. A single planarized deposition of polysilicon is made over the entire surface giving a single contact. With a contact on the backside of the structure, the structure simplifies to a two terminal diode. Furthermore, to simplify the process a geometric etch is used to form the trench prior to oxidation. This gives a square bottomed trench rather than a more physical rounded shape.

A snapshot of the deck used for the 2D experiment inside VWF is shown in Figure 2. The deck is highly parameterized to enable easy investigation into the variability of device behaviour.

 

Figure 2. Parameterized process / device deck inside VWF.

 

The width of the thick grown field oxide, the width of the drift, the doping of the drift and the trench depth were used as the variable set. The width of the field oxide was varied between 0.4um and 0.8um in three steps. The width of the drift was also varied between 0.4um and 0.8um in 3 steps. The drift region doping was varied between 8E15cm-3 and 5E16cm-3 in 4 steps. Finally, the thick oxide trench depth was varied between 4.5um and 6.5um in 3 steps. This gives a total of 108 individual structures, process and device simulations.

The tree generated from these splits in the VWF DOE is shown in Figure 3.

Figure 3. Split tree in VWF showing the different variables used.

 

An exportable worksheet is created from the split parameters. The EXTRACT command is used inside the deck to automate the extraction of the breakdown voltage from the electrical simulations. The extracted data is automatically appended to the worksheet thus enabling easy cross referencing between variables and device performance. Further, more detailed analysis can be undertaken through exporting the data into Silvaco’s Statistical Parameter and Yield Analysis Tool (SPAYN) or to a third party data analysis tool. The worksheet complete with extracted breakdown voltages is shown in Figure 4.

 

Figure 4. Fully populated worksheet for the VWF VLOCOS DOE showing variables and extracted breakdown voltage data.

 

Classically there are three modes of failure with VLOCOS devices, similarly to RESURF structures. Firstly, when the amount of charge in the drift is too high, the drift region is not fully depleted before avalanche multiplication is induced. Breakdown then occurs at the P-Base / N-Drift junction. Secondly, if the charge in the drift region is too low then the drift is rapidly depleted, the dominating electric field spike will occur at the bottom of the trench, on the corner, inducing avalanche multiplication. Finally, an optimally designed device would breakdown with a box shaped electric field profile running down the edge of the thick oxide with impact multiplication simultaneously induced at both the P-Base / N-Drift junction and the bottom corner of the thick field oxide.

Shown in Figure 5 is a typical set of trade-off curves. The width of the field oxide is set at 0.6 um, the depth of the thick oxide is set at 5.5um. Three curves are shown representing three different drift region widths, 0.4um, 0.6um and 0.8um. The breakdown voltage is plotted against N-Drift doping.

Figure 5. Breakdown voltage versus N-Drift doping trade-off curves for three different drift widths.

 

Shown in Figure 6 are 2D contour plots of impaction ionisation from three of the structures shown in Figure 5 with a drift width of 0.8um and doping of 8E15cm-3, 2E16 cm-3 and 5E16 cm-3. These three structures demonstrate the three failure modes discussed earlier. The N-Drift charge for structure on the left is too low, with the drift region depleted too rapidly. As such, breakdown occurs at the bottom of the thick trench. The N-Drift charge for the structure on the right is too high, with the drift region unable to fully deplete, breakdown occurs at the P-Base / N-Drift junction. The optimal design for the parameters considered in this instance is in the middle, where breakdown simultaneously occurs at the P-Base / N-Drift junction and at the bottom corner of the thick trench.

The different breakdown modes can be further understood from Figure 7. Figure 7 shows 1D cutlines of electric field for the three devices shown in Figure 6. The cutlines are taken vertically through the drift region close to the thick oxide. The breakdown modes can clearly been seen from these plots. Excessive depletion of the drift and therefore sub-optimal breakdown is shown by the red curve (N-Drift, 8E15cm-3), the electric field spike occurs at the bottom of the thick oxide. Retarded depletion, the spike moves to the P-Base / N-Drift junction (blue curve, N-Drift = 5E16cm-3). Finally, the optimally depleted drift with simultaneous peaks occurring at both the P-Base / N-Drift junction and at the thick field oxide bottom corner (green curve).

Figure 6. Impact ionisation contour plots showing the three different failure modes. (left) N-Drift charge too low, with breakdown at the trench bottom (centre) optimum drift charge with simultaneous breakdown at trench bottom and P-Base / N-Drift junction (right) excessive drift charge with breakdown at the P-Base / N-Drift junction.

 

Figure 7. 1D cutlines of electric field taken vertically, close to the thick oxide for the structures shown in Figure 6 highlighting the electric field peaks for the different failure modes.

 

The complete set of 2D breakdown data has now been logged. The next phase of the investigation is to expand the structure design out into 3D and consider different corner designs; the 2D data can then be used as a baseline reference.

 

3D Oxidation of Corner Designs

Transitioning from a 2D process simulation to a 3D process simulation is an elementary task in Victory Process. The user simply needs to set the desired 3D workspace co-ordinates, all other statements are common.

Three different corner designs are considered, a sharp 90 degree corner (“Right”), a 45 degree chamfered corner (“Cut”) and a rounded corner (“Round”). These layout designs are used on both internal and external silicon corners, giving a total of 6 corner design variations. The same split parameters used in the 2D simulations are used in the 3D simulations, subjecting each corner design to 108 different permutations.

 

Internal Corners

The first set of three designs are based around the silicon N-Drift forming an internal corner. A sample “Right” structure is shown in Figure 8a. With the polysilicon gate contact and the grown oxide stripped away for visualization, this gives the structure shown in Figure 8b, showing just the silicon.

Figure 8a. Sample 3D “Right” structure on an internal silicon corner.

 

 
Figure 8b. Polysilicon and grown thermal oxide stripped away for visualization from Figure 8a showing the internal corner formed by the silicon and the effect on the silicon consumed by the thermal oxidation.

 

Stripping off the polysilicon and oxide for visualization purposes, a sample “Cut” structure is shown in Figure 9 and a sample “Round” structure is shown in Figure 10.

Figure 9. A sample “Cut” structure on an internal corner with polysilicon and oxide stripped away for visualization.

 

Figure 10. A sample “Round” structure on an internal corner with polysilicon and oxide stripped away for visualization.

 

The starting shape of the trench, before oxidation, is quite evident at the top surface of the structure (where the thin gate oxide resides and minimal silicon consumption via oxidation has occured). Taking a cutplane through each of the three structures as indicated in Figure 11 enables us to compare the resulting corner shapes pre and post field oxidation.

Figure 11Figure 11. Cutplane location through thick field oxide on sample 3D structure.

The pre-oxidation material boundaries for silicon and oxide (polysilicon boundary removed for clarity) from the cutplane location indicated in Figure 11 are shown in Figure 12. The post oxidation boundaries are shown in Figure 13.

Figure 12. Pre-oxidation oxide / silicon material boundaries for the three corner designs.

 

Figure 13. Post-oxidation oxide / silicon material boundaries for the three corner designs.

 

Post oxidation, the corner shape definition is reduced somewhat due to the eating of the silicon. However the resulting oxide / silicon interfaces for the three different layouts still maintain uniqueness. The true effect can only be understood once electrical simulations are performed on the structures, as will be discussed later in this article.

 

External Corners

The previous designs all centred on structures where the silicon formed an internal corner. For many layout designs, such as those that use a racetrack type layout the external corner of the trench must also be considered. Inverting the designs yields structures where the silicon forms an external corner. The same corner design concepts have been applied to this layout.

Shown in Figure 14 is the “Right” corner design on an external silicon corner. Figure 15 shows the reverse side of the same structure yet with the polysilicon and oxide removed for visualization. Figure 16 and 17 show the stripped out view for the external “Round” and “Cut” corner layouts respectively.

Figure 14. Sample 3D “Right” structure on an external silicon corner.

 

Figure 15. Polysilicon and grown thermal oxide stripped away from Figure 14 for visualization showing the external corner formed by the silicon and the effect on the silicon eaten by the thermal oxidation.

 

Figure 16. A sample “Round” structure on an external corner with polysilicon and oxide stripped away for visualization.

 

Figure 17. A sample “Cut” structure on an external corner with polysilicon and oxide stripped away for visualization.

 

 

Electrical Simulations

The demands made on a mesh are often different for process simulation than they are for device simulation. Once the process simulation has been executed, the structure is automatically exported into Victory Device for electrical simulation. During the export stage, a new mesh is created. Exporting the structure and creating a new mesh gives us the opportunity to define a mesh more suitable for device simulation. For example, in device simulation we would typically want a fine mesh underneath the MOS gate oxide to accurately capture the inversion channel, where as in process simulation, this region might not necessarily be a concern.

The device export algorithm is a unified, fully 3D, Delaunay approach for volume mesh generation. It uses the restricted Delaunay triangulation of the vertices with respect to the high resolution surface geometry produced during process simulation. The restricted Delaunay triangulation is a special subset of the triangles which compose the resulting 3D device mesh, it is those triangles whose dual Voronoi edges intersect the input surface geometry. By refining the 3D mesh using careful rules, these restricted Delaunay triangles can be made to capture the surface geometry with arbitrarily high fidelity. By construction, these surface remeshes are simultaneously embedded within a high-quality volumetric mesh.

The meshing scheme is robust and feature rich, the user can refine on junctions, doping, distance to material interfaces, local refinement can also be added via means of boxes, spheres, cones and columns, to name a few of the options. Shown in Figure 18 is a sample exported structure.

Figure 18. Exported sample “Right” structure showing mesh for electrical simulations.

 

The same meshing refinement scheme was applied to all of the structures considered in this article. The scheme is as follows: a coarse base mesh was first defined, refinement on distance to interface was then added, the target interface was the Polysilicon / Oxide interface. This yields a fine mesh in the silicon adjacent to the thin oxide, where the distance to interface is small and a slightly coarser mesh in the silicon near the thick oxide where the distance to polysilicon / oxide interface is larger. This is a perfect scheme to ensure accurate MOS channel and drift depletion prediction. Refinement on junction was then added so as to accurately capture the P-Base / N-Drift junction. Finally box refinement was applied to the step transition between the N-Drift / N+ Drain. The meshing coarsens with distance from the box to that of the base mesh. The starting density and distance are all user defined parameters. Shown in Figure 19 is the structure of Figure 18 but additionally with the doping displayed, highlighting the localised refinement on doping and junction.

 

Figure 19. Doping contours displayed for the structure of Figure 18.

 

Sample breakdown curves are shown in Figure 20. The data showed is a function of thick oxide trench depth for the external “Cut” corner design combined with equivalent 2D data. For the design considered here the effect on breakdown voltage is quite pronounced.

Figure 20. Sample breakdown curves for 3 “Cut” structures and equivalent 2D structures.

 

The failure modes for the 3D structures are identical to the 2D failure modes discussed earlier. A sample is shown in Figure 21a, where the drift charge is too low – hence thick oxide bottom corner failure, Figure 21b, with optimal drift charge, hence simultaneous failure at the P-Base / N-Drift junction and the trench corner and finally excessive drift charge hence breakdown at the P-Base / N-Drift junction, as shown in Figure 21c.

Figure 21a. Sample “Cut” (internal) corner showing impact ionisation failure at the bottom of the trench corner in the silicon due to too low drift charge.

 

Figure 21b. Sample “Cut” (internal) corner showing impact ionisation failure simultaneously at the bottom of the trench corner in the silicon and at the P-Base / N-Drift junction due to optimized drift charge.

 

Figure 21c. Sample “Cut” (internal) corner showing impact ionisation failure at the P-Base / N-Drift junction in the silicon due to too high drift charge.

 

Shown in Figure 22 is a BV trade-off curve against drift doping for the three different layout designs on an internal corner. There is a slight trend in design with the “Round” design giving a marginally higher breakdown voltage than the “Cut” which in-turn gives a slightly high breakdown voltage than the “Right” design.

Figure Figure 22. Breakdown voltage as a function of N-Drift doping for a drift width of 0.6um and thick oxide trench depth of 5.5um for the three different (internal) corner designs..

Shown in Figure 23 is a breakdown voltage / N-Drift doping trade-off curve for the “Right” corner design and three different drift widths. Optimum N-Drift charge can either be achieve through a fixed width and variation in doping or a fixed doping and variation in width. For the doping range considered, a maximum BV of 110V is achieved here for a drift width of 0.6um and doping of 2E16cm-3. The curves imply that a further reduction in doping for a drift width of 0.8um might enable an increase in breakdown voltage but it must be born in mind that this will cause an increase in the on-state losses due to the increased drift resistance, the effect being a direct reference to the breakdown voltage / on-state trade-off curve discussed in the introduction.

Figure 23. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the “Right” corner design and three different drift region widths.

 

Shown in Figure 24 is the breakdown voltage / N-Drift doping trade-off curve for the three different corner designs. Similarly to the internal corner designs, a design layout trend can be seen with the “Right” design showing the optimum breakdown, followed by the “Cut” and then the “Round”. Interestingly, this is the opposite trend to the internal corner design. Overall for the designs considered there is a noticeable reduction in breakdown voltage. No peak in the trade-off is observed, the curve suggests that the doping can be further increased. For the external corner design, when considering this small layout, there is actually three depletion regions working on the N-Drift, the P-Base / Drift junction, as is standard, but this layout also has two thick oxide trenches perpendicular to one another, thus enhancing the depletion. Which in-turn means a high charge can be set in the N-drift region for an optimum BV.

Figure 24. Breakdown voltage as a function of N-Drift doping for a drift width of 0.6um and thick oxide trench depth of 5.5um for the three different (external) corner designs.

 

Shown in Figure 25 are the Breakdown Voltage / N-Drift trade-off curves for the “Right” external corner design as a function of drift width. This further highlights that due to the two perpendicular thick field trench oxide depletion regions operating on the drift region then the drift region can sustain a higher charge for optimum breakdown.

Figure 25. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the “Right” design and three different drift region widths.

 

Shown in Figure 26 are the Breakdown Voltage / N-Drift trade-off curves for the “Round” internal corner design and its equivalent 2D structure. It is quite clear from this plot that it is very important to consider the corner design in the layout. Below a certain N-Drift doping level, the corner design actually enhances the breakdown voltage. Increasing the N-Drift doping leads to a reduction in BV in comparison to the 2D designs, as would typically be considered.

Figure 26. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the “Round” corner design and equivalent 2D structure.

 

Shown in Figure 27 are the Breakdown Voltage / N-Drift trade-off curves for the “Round” external corner design and its equivalent 2D structure. Similar observations can be made to the internal corner design, except in this instance the trend is reversed. It is found that with higher drift charge external corner design shows improved breakdown behaviour. Below a certain drift charge the external corner designs show reduced breakdown behaviour.

Figure 27. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the “Round” corner design and equivalent 2D structure.

 

When considering a small device segment, then corner effects can dominate the simulated characteristics. This is acceptable if the small segment wholly represents the practical device. However, this is not necessarily the case. A complete device is made up of several different corner regions (internal, external etc) and long stretches that are essentially 2D. The lowest breakdown voltage from each of these different areas will be the device’s BV limit.

This is shown in Figure 28. Consider the breakdown voltage at an N-Drift doping of 2E16cm-3, the “Round” structure actually shows a higher breakdown voltage than the 2D equivalent. This is because of the small device size, the corner effects dominating the behaviour. If this design is used in the chip with long, essentially 2D trenches running perpendicularly, away from the corner then the actual breakdown voltage will be lower and will be that of the 2D equivalent structure (red curve). This is because when we move away from the corner, the corner effects no longer dominate and the 2D layout limits the BV. This is shown by the “Large Area Round” (blue) curve in Figure 28.

Figure 28. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the “Round” corner design and equivalent 2D structure.

For the “Large Area Round” structures, the 2D device length, as shown in Figure 29 was increased from 0.8um to 1.8um. Consequently the large area devices show breakdown closer to that of the equivalent 2D device as the corner effect is less dominant and the characteristics tend to that of the 2D device BV limit.

Figure 29. “Large Area Round” structure with polysilicon set to transparent showing the increased dimension in comparison to the devices used previously.

 

Large Area, High Speed Process Emulation for Layout Verification

Once the optimised design is identified through rigorous physical simulation, the next phase is to design the layout. Although the engineer has design rules to follow, it is incredibly useful if the whole chip layout can be simulated. This helps the engineer visualize the layout, communicate the designs and to obtain feedback from colleagues.

Shown in Figure 30 is a quarter cell layout of a complete VLOCOS chip design including termination and deep isolation trenches as seen in [4]. The active trenches can be seen on the right, running horizontally, they are surrounded by the termination and isolation trenches, running vertically on the left and continuing horizontally across the top. The quarter cell is approximately 35 x 35 um with 9 active device trenches approximately 25um long and encircling termination and deep isolation trenches.

Figure 30. GDS layout of a quarter of a full chip.

 

It is quite possible to undertake large area physical simulations, as shown in Figure 31a. Figure 31a shows a section of the full cell design with 2 active trenches, surrounded by a termination trench. Figure 31b shows the same structure but with the polysilicon removed showing the corners and oxide grown through physical simulations. The simulation domain for the example is 10um x 10um and uses the same process sequence as in the previous sections.

Figure 31a. Large area physical simulation of a portion of the full cell design with two active trenches, surrounded by the termination trench.

 

Figure 31b. As Figure 31a but with the polysilicon removed for clarity showing the grown active and termination oxides.

 

However, for simple visualization, rigorous physical simulation is not required. Physical process steps can be replaced by steps that emulate the process step, where the step is defined by geometric parameters, such as thickness and coverage, oxidation can be simplified to an etch of the silicon (to approximate the silicon consumption during oxidation) and oxide deposit, to emulate the oxide growth.

Victory has two modes of operation: Process Mode and Cell Mode. Process Mode was used earlier in this article. Process Mode is optimised for accurate physical simulations whereas Cell Mode is optimised for high speed, large area simulations with focus more on emulation, rather than physical simulation. Deck structure and syntax is common between the two, all the user needs to do is initialise the deck to run in Process Mode or Cell Mode. Obviously physical steps such as oxidation must be suitably adjusted for. Having common syntax makes such a task easy for the engineer as there is no need to learn different tools, syntax or working environments. Call mode structures are not limited for just visualization use, they can also be exported and electrically simulated.

The pseudo-realistic emulated process sequence used here only considers the layout geometry, included in this simulation were contact etches, one via and two metal masks. The quarter cell was simulated in 60 seconds on an “average” desktop machine, the speed coming from the large area, optimised meshing algorithms. The mesh in this instance is the minimum unstructured mesh needed to represent the geometry, no refinement was included.

Shown in Figure 32 is the quarter cell produced from the from the emulated process flow in cell mode, the ends of the active trenches can be seen on the right, with the termination and isolations trenches surrounding.

Figure 32 Quarter cell from the emulated process flow.

 

During export additional manipulation of the structure can be undertaken. For example: sections of the complete structure can be cropped off, material regions can be split and the structure can be mirrored. The latter is particularly useful if the user wishes to take advantage of structural symmetry, as is the case here. The quarter cell of the emulated process was mirrored on both axis during export to give a full cell, the resulting structure is shown in Figure 33, with the top metal layers set to transparent. Figure 34 shows the same structure but from the underside with the silicon set to transparent and the isolation trench removed for visualization, displaying the active and termination trenches.

Figure 33. Mirrored quarter cell, producing full emulated cell. Top metal layers set to transparent.

 

Figure 34. Underside of the mirrored quarter cell, silicon set to transparent and isolation trench removed.

 

 

 

Conclusions

This article has shown that it is vital for the designer to undertake full three dimensional process and device simulations. Without such simulations, and limiting to 2D simulations, device characteristics can be critically overestimated.

This article also demonstrated how high speed, large area, full chip process emulation can be achieved for visualization and design verification.

 

Acknowledgments

The authors would like to acknowledge the support from the “E2SG” Energy to Smart Grid Project co-funded by the ENIAC Joint Undertaking under the SUB-PROGRAMME SP3 - Energy Efficiency ENIAC JU Grant Agreement n. 296131, for part of the effort that contributed to this article.

References

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  4. http://www.silvaco.com/tech_lib_TCAD/simulationstandard/ 2009/jul_aug_sep/a2/a2.html
  5. J. Appels and H. Vaes, “HV thin layer devices (RESURF devices)”, International Electron Devices Meeting Technical. Digest, 1979, pp. 238-241.
  6. T. Fujihira, “Theory of Semiconductor Superjunction Devices”, Japanese. Journal of Applied Physics, 36, 1997 pp. 6254-6262.