Simulations of Deep-Level Transient Spectroscopy for 4H-SiC

 

1. Introduction

Silicon carbide is expected to be an excellent device material as high voltage and low-loss power devices. Recently, SBD (Schottky Barrier Diode) and MOSFET based on silicon carbide have been realized [1-3], however, those devices have some problems for its reliability and control of the IV characteristics. The problems are related to defects in the bulk and at the interface of insulator/semiconductor. The concentration (~5e12[/cm3]) of the defects is 2 orders higher than that of silicon [4], and so the defects cause degradation of device characteristics. The investigation of the defect property is important for the improvement of the device performance.

The DLTS (Deep Level Transient Spectroscopy) is one of the method used in measuring material properties such as energy levels and electrons and holes capture cross sections. The device simulator: Atlas can specify an energy level and a capture cross section, and then, can simulate the DLTS signal. So, we can calibrate the defect properties to the DLTS measurement data accurately and the derived defect properties can be applied to the simulations of device characteristics.

In this article, we demonstrate device simulations of the DLTS signal for a SBD structure with the Z1/Z2 center trap of carbon-vacancy in the bulk.

 

2. DLTS Measurement

The DLTS measurement can be applied to simple device structures like the PN junction device, the Schottky device and the MOS device as shown in the Figure 1 [5].

 

Figure 1. DLTS measurement applied to simple device structures.

 

The Schottky structure is suitable to the investigation of the traps in the bulk semiconductor with an uniform doping. The DLTS signal can be obtained by the following procedure.

  1. A reverse voltage is applied to a device creating a depletion region. As a result nearly all traps have emitted an electron.
  2. 0V is then applied to this device for a certain time such that nearly all traps have captured an electron. This time is called “pulse time”.
  3. Finally the device is biased back in reverse mode in a very short time and this reverse bias is maintained. As shown in Figure 2, electron emission is time dependent and the relaxation process changes the capacitance. By measuring the difference of capacitance between t1 and t2 you can measure temperature dependence of the capacitance difference. That temperature dependence is called “DLTS” signal.
Figure 2. Procedure to obtain the DLTS signal.

 

3.DLTS Simulation of a Schottky Structure with a Single Trap in the Bulk

The DLTS simulation needs to do transient simulation and AC small signal analysis simultaneously. And the capacitance difference depends on the trap concentration. If the doping of N- is 1e15 level and its trap concentration is less than the order of 1e13 [1/cm3], the capacitance difference becomes less than the order of 1e-19 [F] and it is very small. This simulation needs to calculate the capacitance considerably accurately.

Figure 3. Two DLTS signals.
(Red line: sign=5.6e-14[cm2], Green line: sign=5.6e-15 [cm2])

 

Figure 4. 2D structure of 4H-SiC substrate in right side and 1D doping profile in the left side.

 

Figure 3 shows two results of the DLTS simulation. The simulation condition is described as below.

  • Structure/Electrode as shown in Figure 4

    - 4H-SiC substrate: Depth: 12um,

    Dopant: N- type, concentration: 5e14 [/cm3],
    N+ type concentration: 1e20 [/cm3], by
    distance of 2um from cathode

    - Anode: Schottky barrier height: 1.2 eV

    - Cathode: Ohmic


  • Bulk Trap condition

    - Z1/Z2 center trap due to the carbon vacancy

    - energy level (Ec-Et):0.66 eV

    - density: 1e13 [/cm3]

    - capture cross section (sign): 5.6e-14 [cm2] and 5.6e-15 [cm2]

    - degeneracy: 1


  • Pulse condition

    - pulse voltage: 0V, reverse voltage: -8V

    - pulse time: 10ms

    - t1: 10ms

    - t2: 210ms



  • AC small signal analysis

    - frequency: 1e5 Hz

 

Figure 4 shows the structure used for those simulations. It is formed by 4H-SiC substrate of the depth: 12 um with N-type impurity of 5e14 [/cm3]. It has an anode electrode with schottky contact on the top, and a cathode electrode with ohmic contact on the bottom. The region of 2 um with N-type doping of 1e20 [1/cm3] is put on the bottom. Then, The bulk trap condition is assumed to be the Z1/Z2 center trap due to the carbon vacancy. The energy level, the concentration and the degeneracy of the trap are 0.66eV, 1e13 [1/cm3] and 1, respectively.

The two DLTS signals correspond to the difference of the capture cross sections. The left and right signals were calculated with sign=5.6e-14 [cm2] and 5.6e-15 [cm2], respectively. You can find that larger capture cross section makes lower temperature’s peak position, because the relaxation speed of larger capture cross section becomes faster at a same temperature. A DLTS signal of Figure 3 was obtained by 32 transient simulations including the AC analysis, which were calculated with different temperatures by 5 degrees. Figures 5 and 6 shows 4 transient simulations of the electron emitting process in the temperatures: 280, 300, 310, and 320K. You can see that higher temperature makes shorter relaxation time for the electron emitting process from traps.

Figure 5. Transient simulations of capacitance (sign=5.6e-14 [cm2]).

 

Figure 6. Transient simulations of capacitance (sign=5.6e-15 [cm2]).

 

 

4. Summary

We have demonstrated that the DLTS (Deep Level Transient Spectroscopy) signal can be simulated by the device simulator: Atlas. The DLTS simulation needs the analysis of the very small capacitance difference and Atlas has the function to carry out the transient simulation and the AC small signal analysis simultaneously and accurately.

 

References

  1. T. Sakaguchi et al., Tu-P-59, p.171, ICSCRM 2013
  2. M. Okamoto et al., Mo-1A-4, p.10, ICSCRM 2013
  3. F. Devynck, Thesis, Figure 1.4, p. 8, 2008
  4. T. Hatakeyama et al., Materials Science Forum , pp.477-480, Vols, 740-742, 2013
  5. K. Matsuda, Horiba Technical Reports, “Semiconductor Impurities and Defects Evaluation by ICTS and DLTS”, pp.15-26, No.2, January, 1991