Simulation of Stress Evolution During Semiconductor Device Fabrication



Accurate stress simulation has become a necessary part of performance and reliability analysis of semiconductor devices. In our previous paper [1] we demonstrated that 3D stress simulation of the whole cell provides more accurate prediction of stress effects on device performance than simulation limited to individual devices.

In [1] we used a standard approach which calculates stresses in the final structures with some material regions (“stressors”) having specified values of intrinsic stress. Thus, this approach could be called a ”onestep” model where stresses are calculated only once for a given final structure.

Another approach takes into account stress generation and changes associated with each processing step. Any semiconductor device manufacturing process consists of multiple steps including material layer depositions (in some cases with specific intrinsic stress), etching of the layers or their portions, as well as heating and cooling cycles. It is obvious that stresses in the device structure are changing from step to step because geometry, materials and temperatures are evolving through the process sequence. The more detailed “stepbystep” model calculates stresses after each process step taking into account current geometry, temperature, material properties, as well as stresses generated in the structure during previous steps. This approach can be called the “stress evolution” or “stress history” model.

Obviously, the stress history approach is more time consuming but it definitely provides more accurate results. Some comparisons of stress history and onestep stress simulation results in 2D can be found in papers [2] and [3]. In this paper we analyze 2D and 3D stress evolution using the stress history capability recently implemented in the VICTORY Stress simulator. In the next section we show use of stress history model for accurate stress simulation in a thick deposited stressor film. After that we will demonstrate stress history effects in an interconnect structure. The third section presents the stress history simulation of a FinFET manufacturing process in comparison with the results of our previous paper [1].


Use of Stress Evolution Model for Thick Layer Deposition

Authors of paper [2] suggested that in order to accurately predict stresses in thick layers the process should be considered as a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during this physical deposition process.

Usually the stress in a deposited layer can be found from its curvature by using the well known Stoney formula [4]. This estimated stress value can be then inserted into the system of stress simulation equations while accounting for a factor transforming this value into the hydrostatic stress for both 3D and 2D plain strain models.

Most commercial process and stress simulators consider deposition not as a physical process governed by a time dependent model, but rather a mathematical abstraction; a new layer just appears on the top of the structure. In these simulators the stress equations are solved after a material layer or region has already been added to the structure and not during the physical process of deposition. This onestep approach could not accurately predict stresses built into the deposited layer and in adjacent areas. Simulations and direct comparisons with electrical measurements performed in [2] clearly showed that this onestep model underestimates stresses in the etchstop layer and in the channel area, while the stress evolution model applied to multilayer deposition accurately predicts mobility enhancement in both NMOS and PMOS test transistors.

We use VICTORY Stress to simulate stresses during thick nitride layer deposition over the test structure similar to the test structure of [2]. The deposited layer thickness in case of the onestep model simulation was 160nm. The stress evolution model was applied to a sequence of 20 deposition steps of 8nm layer thickness each. The intrinsic stress value was equal to 1GPa in both simulations. The 2D plane strain model was used in both cases. Both structures were obtained using ATHENA. The stress evolution simulation uses the same structure with 20 layers at each step while the effect of new sublayer deposition is emulated by changing the status of this new sublayer from “nonactive” to “active” material region with the intrinsic stress of 1 GPa. VICTORY Stress then recalculates stresses in the modified structure after each deposition step. The stress distributions obtained by both models are compared in Figure 1 (XXcomponent) and Figure 2 (YYcomponent).


Figure 1. The Sxx distribution for stress evolution model with 20 sublayers (left) and one step model (right).


Figure 2. The Syy distribution for stress evolution model with 20 sublayers (left) and one step model (right).


Our results are similar to those obtained in [2]. In flat areas of deposited layer both models produced similar and essentially uniform stress. In the single layer case nonuniform stress regions appear only near corners of spacer/nitride. However, in the case of multilayer stress history simulation, a highly nonuniform stress field extends diagonally from the spacer/substrate corner to the top of the film. In other words, stresses are significantly higher where the layers are sharply bent. As a result the integrated stresses under the gate appear to be 1.4 – 2 times higher when the stress history method is used. In the case of a single 160 nm layer, the averaged integrated lateral and vertical stresses under the gate are Sxx=0.24GPa and Syy=0.15, respectively. Figure 3 shows how these stresses depend on the number of 8 nm sublayers. When the total thickness reaches 160 nm (20 sublayers) the lateral stress is Sxx=0.325GPa while the vertical stress is Syy=0.28GPa.

Figure 3. The dependence of Sxxand Syystresses (averaged under the gate) on the number of 8nm sublayers.




Figure 4. The geometry and materials of the film stack of interconnect; a) – the whole structure; b) – silicon and metal lines with contact and via.


These results clearly suggest that the multilayer evolution model is preferable for more accurate analysis of stress engineered mobility enhancements.


Stress Evolution Simulation of Interconnects

The manufacture of interconnect layer stacks consists of a sequence of steps of heating up during deposition and cooling down during etching. The materials (metals and dielectrics) used in interconnect structures often have large differences in their thermal expansion coefficients and therefore the thermal mismatch between material layers could result in high levels of tensile stresses and consequently various failure events including voiding and cracking. Usually the stresses generated in an interconnect structure are simulated after the last process step when room temperature is reached.

The authors of paper [3] performed a 2D simulation and analysis of stress history during formation of an interconnect structure. They suggested that it would be interesting to repeat such simulations on 3D and compare the results with 2D plain strain approximation. We use VICTORY Stress to simulate stress evolution in a 3D interconnect structure built using the similar process sequence and geometry, as well as the same material properties as in Table 1 of paper [3].


Table 1. The average stress data (in GPa) in metal layers for 2D and 3D cases.

Note. For 2D the third omitted transversal component was estimated as: Sest=n(Sxx+Syy).


The interconnect structure analyzed in this section was obtained using VICTORY Cell. As we already mentioned above, VICTORY Stress emulates the process sequence by a special capability to designate some materials/regions of the current structure to be “nonactive”. This means that they will either be deposited later or have been etched before the current process step. Also, VICTORY Stress allows user-define material regions to inherit the elastic properties and thermal expansion coefficient of real materials. The last capability makes it possible to consider some parts of a layer to be “nonactive” at a certain step, but later to become a region with real material properties. The elastic properties of those nonactive regions/materials are set as follows: Young modulus is equal to 1Dyn/cm2 , Poisson ratio is equal to zero, and the thermal expansion coefficient is set to zero too. In subsequent discussion we will call these nonactive materials “air”.

  1. Substrate Si region is heated from T1=20C up to T2=400C. All other regions are “air”.
  2. The oxide isolation layer is deposited. The layer consists of two material regions, D1 (oxide) and contact(oxide). The temperature drops from T1=400C to T2=20C.
  3. Etching of contact, which changes inheritance of contact region from oxide to contact(air)), T1=T2=20C.
  4. The structure temperature is increased from T1=20C to T2=450C. After this step the structure consists of Si, D1(oxide) while all other regions are “air”.
  5. The layer contact(W) is deposited and temperature drops from T1=450C to T2=300C for aluminum layer deposition at the next step.
  6. Aluminum deposition: regions metal1(Al) and D2(Al) are deposited now and temperature drops from T1=300C to room temperature T2=20C.
  7. Etching of D2 region: D2(air) at T1=T2=20C.
  8. The structure consisted of D1(oxide), contact(W), metal1(Al), while the rest of the structure are “air” regions, is heated from T1=20C up to T2=400C for subsequent oxide deposition.
  9. The following three regions are filled with oxide D2(oxide), via(oxide), D3 (oxide), and the structure was cooled down from T1=400C to T2=20C;
  10. The via is etched so the via region is now via(air), T1=T2=20C.
  11. The structure consisted of Si, D1(oxide), contact(W), metals(Al), D2(oxide), and D3(oxide) is heated from T1=20C to T2=450C for the tungsten deposition into the via region.
  12. The tungsten deposition into via(W), T1=450C, T2=300C.
  13. Deposition of metal2(Al) and D4(Al) and cool down from T1=300C to T2=20C;
  14. The etch of D4(Al), so now it is D4(air) at room temperature T1=T2=20C.
  15. The structure consisted of Si, D1(oxide), contact(W), D2(oxide), D3(oxide), metal1(Al), metal2(Al) is heated from T1=20C up to T2=400C for the future deposition of passivation nitride layer.
  16. The deposition of D4(nitride) and D5(nitride) and cooling down from T1=400C to T2=20C.

Results of simulations are shown in Figure 5 – Figure 7. To compare our simulations with the results of [3] obtained in the 2D plane strain model we performed full 3D simulation as well as 2D simulation in the cut plane (see Figure 4) which is perpendicular to the y axis and passed through the center of contact/via regions, see Figure 6 and Figure 7. As mentioned in [3] the full 3D simulations may be necessary to find out what are the limitations of the reduced 2D model. The comparison of our 2D and 3D results has proved that the above mentioned choice of the cut plane for the 2D simulation was adequate. Figure 6 demonstrates results of simulations in 3D and 2D (plane strain model) for a lateral stress component (Figure 6a) and for a vertical stress component which is Syy for 2D and Szz for 3D (Figure 6b). The left pictures in Figure 6a and Figure 6b show stresses in the cut plane in a 3D structure while the right pictures show Sxx and Szz stress components of 2D solutions. The resulting stresses shown in these pictures are close to each other. The authors of [3] estimated that in their simulations the average hydrostatic stress was about 0.76GPa (see Figure 2 of [3]). Furthermore, they estimated that the stress levels of two metal layers were very close to each other. Our simulations shown in Figure 6 demonstrate that stress in the second metal layer is little bit higher 0.84 GPa than in the first metal 0.72 GPa. This happens because these layers are surrounded by different dielectric materials, oxide and nitride. The average data of stress components for 2D and 3D cases are summarized in Table 1.

Figure 5. The Sxx distribution at the final step of technology process.




Figure 6. There are the lateral stress component (a) and vertical stress component (b) for 3D case (left structures for both, a) and b)) and for 2d case (right structures for both a) and b)).


We have performed simulations with and without intrinsic stress in some layers. The intrinsic stress values in the oxide dielectric layer, nitride passivation layer, and CVD tungsten layer were 0.1 GPa, 0.3 GPa, and 0.6 Gpa, respectively. These are the same values as in simulations of paper [3]. Our results shown in Figure 7 have supported the conclusion of [3] that “ the intrinsic stresses in surrounding materials have very little effect on metal line stress”. Figure 7a shows Sxx distribution when intrinsic stressed are taken into account. Figure 7b shows the same distribution when intrinsic stresses where not applied. For comparison purposes Figure 7c shows the same distribution obtained with onestep model, see details below. Figure 7d shows 1D distributions along a vertical cut through the metal regions. The red line corresponds to Figure 7a, green line corresponds to Figure 7b, and blue line along corresponds to Figure 7c. Comparisons of stress intensities inside metal regions on Figure 7a and Figure 7b as well red and green profiles in Figure 7d clearly show that stresses inside metal lines are not affected by stresses generated in surrounding regions of the structure. This conclusion makes perfect sense because metal layers have a very high thermal expansion coefficient in comparison with other materials, therefore the relatively small intrinsic stresses in surrounding materials could not noticeably change the stress in metal layers.

Figure 7. Sxx distributions in interconnect structure. Fig. 7a. shows result obtained with the stress history model and intrinsic stress in oxide, nitride and tungsten taken into account. Figure 7b shows result obtained with stress history model but without intrinsic stresses in above mentioned materials. Figure 7c shows result obtained with the onestep model and intrinsic stresses calculated according to Equation 1. Figure 7d is comparison between three above results along vertical cut line through metal regions – red, green, and blue line correspond to Figure 7a, 7b, and 7c, respectively.


As we mentioned above we also use the traditional “one step model” for comparison purposes. For each material region we use the difference between the temperature of each layer deposition and room temperature to calculate the intrinsic stress value of the corresponding materials according the following formula:

Here E=Young modulus, ν=Poisson ratio, α=the thermal expansion coefficient of deposited material and T2=20C (room temperature) and T1 the temperature of the material deposition (see the description of the process steps above).

The Sxx 2D distribution presented in Figure 7d (see also the blue curve in Figure 7d) was calculated using the “one step model” in 2D plane approximation with intrinsic stresses estimated by Eq. (1) for each material. In the regions occupied by metal1 and metal2 layers the stresses are significantly lower than those obtained using the stress history model. In conclusion: the onestep model seriously underestimates stresses in metal lines.


FinFET Simulations

In this section we will investigate the difference between simulation results obtained by “one step” and stress history models applied to a 3D FinFET structure similar to one analyzed in [1]. Two scenarios of process sequences: “via last” and “via first” were considered. Table 2 summarizes regions/materials and their elastic properties used in this simulation.


Table 2. The elastic properties and thermal expansion coefficients of materials, used for simulations (see the Figure 4).


For both scenarios the three types of nitride capping liners were studied: neutral (intrinsic stress S0=0), tensile (S0=1GPa) and compressive (S0=1GPa). The scenarios presented below are just illustrations of simulation methodology. They include only main process steps: deposition at high temperature and etching at room temperature. Some steps are combined together. For example, thin layer “blanket” oxide deposition with subsequent low temperature etching are combined in one step called “gate oxide” deposition. Our simulations confirmed that this can be done without losing any accuracy. As in simulation of interconnects described in the previous section, the regions of the FinFET structure may be filled with different materials or “air” at different steps of the process sequence.

The “via last” case consists of the following nine steps.

  1. The structure consisted of “box”, “nfin”, and “nstressor” regions is heated from T1=20C to T2=920C for subsequent “gate oxide” deposition. All other regions are “air”.
  2. Polysilicon gate deposition and cooling down from T1=520C to T2=320C for subsequent “metal” contact deposition.
  3. The “metal” deposition into contact areas and heating from T=320C to T=820C for subsequent capping layer deposition.
  4. The deposition of “nliner” and “via11” (nitride) regions and heating up from T1=820C to T2=920C for subsequent oxide deposition.
  5. Oxide and “via12”(oxide) regions deposition with cooling down from T1=920 to T2=20C for subsequent etching of vias.
  6. Etch of “via11” and “via12” at room temperature T1=T2=20C so now these regions are filled with “air” via1 (air) and via2(air).
  7. The structure is heated from T1=20C, to T2=320C for subsequent via deposition.
  8. Material “via11”(Al) and “via12”(Al) deposition and the final structure is cooled down from T1=320C to T2=20C.


“Via first” consists of six steps.

  1. The structure consisted of “box”, “nfin”, “nstressor” s heated from T1=20C to T2=920C for subsequent “gate oxide” deposition. All other regions are “air”.a
  2. The deposition of “via11”(Al), “via12”(Al), and “metal”(Al) contact regions and the heating from T1=320C to T2=920C for subsequent gate oxide deposition.
  3. The “gate oxide” region deposition and cooling down from T1=920C to T2=520C for subsequent polysilicon deposition.
  4. Polysilicon gate deposition and cooling down from T1=520C to T2=320C for subsequent “metal” contact deposition.
  5. The deposition of “nliner” and “via11” (nitride) regions and heating up from T1=820C to T2=920C for subsequent oxide deposition.
  6. Oxide deposition and cooling down of final structure from T1=920C to T2=20C.

First we analyze the stress distribution under the gate for the neutral capping layer (S0=0). Figure 8 shows two 2D stress distributions in the central cut of FinFET for “via last” and “via first” scenarios as well as comparisons of 1D stress profiles along different cut lines. The averaged values of the stress components and estimated mobility enhancement factors can be found in the first rows of Table 3 and Table 4. Corresponding values calculated in [1] using fixed intrinsic stresses in nitride are summarized in Table 5 for comparison purposes. It is obvious from Figure 8d and the first columns of Tables 3 and 4 that “via last” scenario results in higher Sxx stresses under the gate (0.304 GPa vs 0.115 GPa). This happens because in the “via first” scenario the metal regions appeared in the structure earlier, relaxed at higher temperature of 920C and subsequently obtained large compressive stresses during final cooling down. As a result the stresses under the gate become less compressive. However, the order of process steps did not affect other stress components. This stress history simulation proves that the 3D effects become significant because the x and y directions are not equivalent during relaxation after key etch steps.

Figure 8. The two Sxx stress distributions of the central cut of FinFET structure are results of simulations of the “via last” and “via first” technology scenario (neutral capping layer). The first 1D plots is Sxx distribution along the vertical cut; the other three are Sxx, Syy and Szz graphs along cut line at z=0.05um in xdirection; red lines correspond to the “via last” case and green lines correspond to the “via first” case.


Table 3. The integrated stress components in the fin under the gate for the FinFET for the “via last” technology, in GPa. Corresponding mobility enhancement factors are unitless and calculated using formulas from [1].


Table 4. The integrated stress components in the fin under the gate for the FinFET for the “via first” technology, in GPa. Corresponding mobility enhancement factors are unitless and calculated using formulas from [1].


Table 5. The integrated stress components in the fin under the gate for the FinFET obtained using the “one step” model as in our paper [1]. Corresponding mobility enhancement factors are unitless and calculated using formulas from [1].T


Figure 9 shows three 2D stress distributions in the central cut of FinFET for “one step” model, “via last” and “via first” scenarios as well as comparisons of 1D stress profiles along the cut line directly under the gate. All three results were obtained at 1GPa stress in nitride regions. The corresponding averaged values of the stress components and estimated mobility enhancement factors can be found in the second rows of Table 3 and Table 4. The simulation data at 1GPa are shown in 10 and summarized in the third row of Table 3 and Table 4. It obvious that stress history results substantially differ from the “onestep” model.

Figure 9. The top three plots from left to right are the 2D Sxx distributions in the central cut plane of FinFET with tensile capping layer (1GPa) simulated with “one step” model, the history stress model for “via last” and “via first”scenarios, correspondingly. Below are three 1D distributions of Sxx, Syy and Szz stress components along cut line in the fin under the gate. The red curves are for the “one step” model, green lines are for the “via last”scenario, and blue lines are for the “via first” scenario.


Figure 10. These plots are the same as in Figure 9 but simulated with compressive capping layer (1GPa).


All above simulations were performed using a 3D structure consisting of approximately 800,000 tetrahedrons. Each simulation run takes just few minutes.



The VICTORY Stress simulator is able to calculate the stress evolution in 2D and 3D structures during multistep semiconductor device processing. Therefore it allows accurate prediction of how processing conditions at each step, as well as the sequence of the steps, affect the device or interconnect characteristics and reliability.



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  2. K.V. Loiko, V. Adams, D.Tekleab, B.Winstead, X.Z. Bo, P.Grudowski, S. Goktepeli, S. Filipiak, B. Goolsby, V.Kolagunta and M.C. Foisy, “MultiLayer Model for Stressor Film Deposition”, SISPAD, 2006, p.123
  3. Jin Lee, Anne Sauter Mack, “Finite Element Simulation of a Stress History During the Manufacturing Process of Thin Stacks in VLSI Structures”, IEEE, V. 11, N. 3, 1998, p.458.
  4. Stoney, G.G., The Tension of Metallic Films Deposited by Electrolysis, Proc. Roy. Soc., vol.A82, (1909) p.172175.


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