Simulation of Stresses and Mobility Enhancement Factors in 3D Inverter Cell
Introduction
The analysis and characterization of stress effects have become an integral part of semiconductor technology and device design. In a typical semiconductor process flow the stresses are generated primarily due to volume expansion or contraction of the adjacent materials during temperature variations. Stresses could also be generated during oxidation, silicidation, etching, and deposition processes or due to lattice expansion or contraction after introducing large doses of dopants. Simulation of process induced stresses is an important component of traditional TCAD analysis since these stresses could have adverse or positive effect on individual process steps or on final device characteristics.
It is even more important to accurately simulate and optimize socalled stress engineering processes. Stress engineering is a deliberate introduction of stresses into device structures with a goal to enhance carrier mobility and consequently device performance. The most common method of introducing desirable stresses into a transistor channel region is deposition of high tensile or high compressive films of nitride type materials [1]. This method is called the global stress engineering. Another method introduces stresses by formation of locally strained source/drain regions [25]. These local regions could be created, for example, by epitaxial growth of compositional Si:Ge or Si:C materials.
In this paper we use 3D simulator VICTORY Stress to analyze stress effects on carrier mobilities of individual nFinFET and pFinFET devices as well as on characteristics of an inverter cell consisting of one nFinFET and two pFinFETs. The stresses in a whole cell are analyzed in this paper for the first time. Typically stress simulations have been preformed just in separate devices. However, it appears that proximity effects may require simulation of the whole cell. Both global and local methods of stress engineering are considered for each device type.
Verification of VICTORY Stress
It is very difficult to reliably estimate absolute accuracy of a 3D stress simulation. We have performed numerous simulations for different device structures using VICTORY Stress and compared the results with simulations and conclusions of other authors [1] – [6]. We will discuss some details of these comparisons elsewhere. Here we just want to note that in most cases VICTORY Stress simulations correspond to measured and numerical results of these papers. As an example we would like to highlight comparisons with MicroRaman Spectroscopy stress field measurements presented in [2]. VICTORY Stress simulation results shown in Figure 1a and Figure 1b quantitatively confirm conclusions of paper [2] that locally strained recessed Si_{0.8}Ge_{0.2} S/D regions induce compressive stress in the MOSFET channels between them and that the absolute value of this stress increases with decreased spacing between these recessed regions and with increased thickness of these regions.
Figure 1a. The XXstress field and its profile along the cut at 30nm below Si surface for a test structure with series of recessed Si_{0.8}Ge_{0.2} regions of 0.15 micron thickness and gate areas with varying gate lengths (8, 4, 2, 1, and 0.5 microns). 
Figure 1b. The same as Figure 1a only with the recessed Si_{0.8}Ge_{0.2} regions of 0.3 micron thickness. 
Motivation for Stress Simulation in An Inverter Cell
Many papers on stress engineering (see, for example, [1][6]) used numerical simulation to analyze the effect of different stress implementation methods on carrier mobilities for various FET device configurations (classical CMOS, SOI, FinFET etc.). The conclusions of these simulations are actually fairly obvious: both thin film liners (compressed for ptype devices, tensile for ntype devices) and stressed S/D regions (compressed for ptype devices, tensile for ntype devices) implemented near the gate significantly increase corresponding carrier mobility of all types of devices. Simulations and measurements of electrical characteristics prove this conclusion. However , to our knowledge, there are no published stress simulation results for a cell consisting of several individual devices located in proximity of each other. We believe that it is important to know how stresses from different sources interact with each other in areas of interest, for example, under the gates of various devices in a cell. These interaction effects could be even more pronounced when CDs of individual devices and distances between them scale down. In order to investigate these effects we used VICTORY Stress simulations in a FinFET inverter test structure.
The inverter cell consists of three FinFETs: one FinFET is of ntype and the other two are ptype devices located parallel to each other as shown on the layout (Figure 2). The resulting whole cell structure was obtained from this layout using VICTORY Cell 3D process simulator and shown in Figure 3. A partial “npcell” consisting of one ntype FinFET and one ptype FinFET in sequence (see Figure 4) as well as individual ntype FinFET (Figure 5) and ptype FinFET (Figure 6) devices were also obtained by VICTORY Cell using corresponding portions of the layout.
Figure 2. Layout of the inverter cell. 
Figure 3. 3D view of the whole inverter cell. 
Figure 4. 3D view of the npcell. The liner stressors are hidden to demonstrate the simulation grid in the fin area. 
Figure 5. 3D view of nFinFET device. Only BOX substrate and active area of device with simulation grid are shown. 
Figure 6. 3D view of pFinFET device with stress distribution in the fin area. 
Simulation Results
The 3D stress distributions for all four structures were simulated with the following values of intrinsic stress: 1GPa (tensile) for liners and S/D regions in ntype device and 1GPa (compressive) for both types of stressors in ptype devices. This value of intrinsic stress roughly corresponds to compressive Si90Ge10 and tensile Si99 C01 (Young modulus E=187 GPa and Poisson ratio ν= 0.28 were used in these estimations). The elastic properties of the liners correspond to those of Si3N4. The elastic properties of silicon fins correspond to those of isotropic silicon. Though VICTORY Stress can take into account anisotropic elastic properties of silicon and other materials, this anisotropy has a very small effect in silicon because its tensor of elasticity varies insignificantly for different crystallographic orientations. However, the mobility enhancements noticeably depend on silicon crystal orientation because the tensor of piezoelectricity varies significantly for different crystallographic orientation. The following equations were used for the n and p mobility enhancement factors for (100)/<100> and (110)/<100> crystallographic orientations in silicon:
μ_{n}^{100} =1.0 − (–1. 022* σ_{xx} +0 .534* σ_{yy}+0 .534* σ_{zz})
μ_{n}^{110} =1.0 – (−0.311* σ_{xx} 0.175* σ_{yy}+0 .534* σ_{zz})
μ_{p}^{100} =1.0 – (0. 066* σ_{xx} 0.011* σ_{yy}0.011* σ_{zz})
μ_{p}^{110} =1.0 –(0.718* σ_{xx} 0.663* σ_{yy}0.011* σ_{zz})
In these equations the stresses are in units of GPa and coefficients of piezoresistivity are in 1/GPa.
Tables 1 and 2 summarize the stress values σ_{xx}, σ_{yy}, and σ_{zz}, and mobility enhancement factors µ_{n}^{100}, µ_{n}^{110}, µ_{p}^{100}, and µ_{p}^{110}, which were averaged by integration of corresponding stress distributions along the cut 5nm below the finoxide boundary under the gate as shown, for example, in Figure 7. Table 1 shows results for liner stressors and Table 2 shows results for S/D stressors. Note, that “p1” corresponds to ptype device which is aligned with ntype device in the whole cell, while “p2” corresponds to the second ptype device.
Figure 7. 2D stress distribution through center of pFinFET and 1D stress distribution at the top of pFin under the gate used for calculation of average stress. 
Type of cell or FinFET  Type of FinFET 
σ_{xx}, GPa 
σ_{yy}, GPa 
σ_{zz}, GPa 
µ_{n}^{100} 
µ_{n}^{110} 
µ_{p}^{100} 
µ_{p}^{110} 
Whole cell  n 
0.055 
0.251 
0.246 
1.0535 
1.1921 
n/a 
n/a 
p1 
0.014 
0.178 
0.238 
n/a 
n/a 
0.991 
0.875 

p2 
0.0009 
0.181 
0.239 
n/a 
n/a 
1.000 
0.883 

npcell  n 
0.0107 
0.12 
0.236 
1.051 
1.144 
n/a 
n/a 
p 
0.0124 
0.12 
0.236 
n/a 
n/a 
0.993 
0.914 

nFinFET  n 
0.215 
0.234  0.228 
1.217 
1.23 
n/a 
n/a 
pFinFET  p 
0.214 
0.234 
0.228 
n/a 
n/a 
1.142 
1.001 
Type of cell or FinFET  Type of FinFET 
σ_{xx}, GPa 
σ_{yy}, GPa 
σ_{zz}, GPa 
µ_{n}^{100} 
µ_{n}^{110} 
µ_{p}^{100} 
µ_{p}^{110} 
Whole cell  n

0.276 
0.073 
0.034 
1.34 
1.091 
n/a 
n/a 
p1 
0.279 
0.062 
0.035 
n/a 
n/a 
1.187 
1.242 

p2

0.279 
0.064 
0.035 
n/a 
n/a 
1.187 
1.242 

npcell  n

0.273 
0.06 
0.036 
1.33 
1.094 
n/a 
n/a 
p 
0.275 
0.06 
0.035 
n/a 
n/a 
1.187 
1.242 

nFinFET  n 
0.278 
0.058 
0.0355 
1.334 
1.095 
n/a 
n/a 
pFinFET  p 
0.279 
0.058 
0.0354 
n/a 
n/a 
1.187 
1.242 
From numerical data summarized in Table 1 it is clear that the stresses and mobility enhancements for each device in the whole cell (rows 1, 2, and 3) and in the npcell (rows 4 and 5) noticeably differ from stresses and enhancements obtained by simulation of individual devices (rows 6 and 7). This happens due to interaction between nliner and pliner.
Table 2 doesn’t demonstrate significant difference between results obtained for cells and individual devices. This is apparently because of the local nature of S/D stressors in this test configuration. However, the interaction effect could be more pronounced for different S/D stressor configurations or for more dense cell layouts.
Conclusions
We demonstrated that a combination of 3D process simulator VICTORY Cell and 3D stress simulator VICTORY Stress allows fast and accurate stress analysis of complex cell structures. The largest structure in this study consisted of more than 4 million tetrahedra and it took just 10 – 20 minutes to simulate the formation of the structure and calculate stress fields in it. We clearly showed that in some cases it is important to simulate stresses not just in an individual device’s structures but in the whole cell. The exceptional speed of VICTORY Cell and VICTORY Stress allows the performance of detailed analysis and optimization of various stress engineering schemes by varying geometrical characteristics, orientation, CDs, and material composition of each device as well as by changing location and density of the individual devices inside the cell layout.
References
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 F. Nouri, et al, “A Systematic Study of Tradeoffs in Engineering A Locally Strained pMOSFET”, IEDM Techn. Dig., 2004, p.1055
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