3D TFT Simulation


1. Introduction

Both flexible and touch panel displays have become popular for portable applications. To meet various functional requirements, system-on-panel (SOP) design has become essential [1] and different layouts as well as material have been used in the last few years [2]. Although various design and physical effects [3-5] have been successfully analyzed using 2D Technology-Computer-Aided-Design (TCAD) software, it becomes important to start to analyze and predict device performance dependent on layout effect with 3D TCAD.

In this paper, we simulate different type of TFT devices and we show the influence of key physical models on IV curves for calibration purpose.


2. Physical Models

Disordered materials contain a large number of defect states within the band gap of the material. To accurately model devices made of polycrystalline or amorphous materials, we need to take these defects into account.

The total DOS is a combination of two exponentially decaying band tail states and two Gaussian distributions of mid-gap states. [6].

Here, E is the trap energy, Ec is the conduction band energy, Ev is the valence band energy and the subscripts (T, G, A, D) stand for Tail, Gaussian (deep level), Acceptor and Donor states respectively.

For an exponential tail distribution, the DOS is described by its conduction and valence band edge intercept densities (NTA and NTD), and by its characteristic decay energy (WTA and WTD). For Gaussian distributions, the DOS is described by its total density of states (NGA and NGD), its characteristic decay energy (WGA and WGD), and its peak energy/peak distribution (EGA and EGD).

SIGTAE and SIGGAE are the electron capture cross-sections for the acceptor tail and Gaussian states respectively. SIGTAH and SIGGAH are the hole capture cross-sections for the acceptor tail and Gaussian states respectively. SIGTDE, SIGGDE, SIGGDH, and SIGGDH are the equivalents for donor states.

In addition to the defect model, Shockley-Read-Hall recombination, band to band tunneling, trap assisted tunneling and impact ionization models can be used to accurately simulate TFT de vices.

We show in Figure 1 the influence of the defect and interface defect on IdVg curve in reverse at low vds. Note also that the low current leakage at negative Vgs is very well modeled using the extended precision version of ATLAS.

Figure 1. Effect of Defect on IdVg curve in reverse.

In Figure 2 we show the effect of physical models also on IdVg curve in reverse but this time at high Vds. We can see the impact of the band to band tunneling model as well as the trap assisted tunneling model.

Figure 2. Effect of physical models on IdVg curve in reverse.

These physical models mentioned above are the key for successful simulation of TFT devices.


3. Poly-Si 3D TFT Simulation

We simulated an n-type Poly-Si TFTs. A 3D layout driven process simulation was performed. The resulting 3D structure is shown in Figure 3 (a) and the 2D slice in Figure 3 (b).

Figure 3. (a) 3D poly-Si TFTs (b) 2D cross-section cut from 3D TFTs.


3D device simulation results are compared to measurement in Figure 4a and 4b.

Figure 4a. IdVg simulation, comparison with measurement.


Figure 4b. IdVd simulation, comparison with measurement.

The advantage of simulation is that we can investigate and analyze physical quantities inside the 3D structure. Figure 5 a and b show the 3D distribution of potential and impact ionization rate. This helps the designer to diagnose possible problem or simply optimize the design.

Figure 5a. 3D potential distribution and isosurface (Vg=2V, Vd=12V).


Figure 5b. 3D isosurface of impact ionization probability around the LDD and near drain contact.




4. A-Si:H 3D TFT Simulation

A n-type A-Si:H TFTs was simulated. Here as well the layout was used as an input to the 3D process simulator. The resulting 3D structure is shown in Figure 6. IdVg as a function of Vg as well as IdVd as a function of Vg were simulated and are shown in Figure 7 and 8. It is also very interesting to notice that due to the specific 3D effect the simulated curve when we reverse the source and the drain are different as shown in Figure 9.

Figure 6. 3D A-Si:H TFT structure.


Figure 7. 3D A-SiC:H IdVg simulation.


Figure 8. 3D A-SiC:H IdVd simulation with reverse source and drain.


Figure 9. 3D A-SiC:H IdVd simulation with reverse source and drain.


5. 3D ZnO bottom gate TFT Simulation

IdVg and IdVd simulations of a IGZO (indium galium zinc oxide) TFT device were performed and are shown in Figure 11. The corresponding structure is shown in Figure 10.


6. Gate Driver TFT Simulation

Figure 10. 3D IGZO TFT structure.


Figure 11. 3D IGZO IdVg and IdVd simulation.


A conventional LCD needs gate drivers. The gate drivers are integrated in the LCD process itself to cut down the cost. 3D TCAD simulation can thus be useful for optimization purposes. Including the gate driver into the simulation allow early detection of possible undesirable electrical as well as thermal effects which may deteriorate the efficiency of driving the gate. Figure 12 shows an example of a top-gate metal oxide TFT simulation.

Figure 12a. 3D structure.


Figure 12b. 3D electron distribution at turn-on bias.


Figure 12c. 2D electron distribution cut from 3D file.



7. Conclusion

We simulated different types of TFT with 3D process and device simulation. Although 2D device simulation is very useful , layout effect is neglected. We have shown that SILVACO provides a complete 3D process and device simulation solution to address future challenges in TFT design. Using SILVACO tools, designers can accelerate and optimize the development of TFTs for next generation display technologies.



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  2. L.-W Chu and P.-T. Liu: J. Disp. Tech. 7 (2011) 657.
  3. H.-H. Hsieh et al., SID Technical Digest (2008) 425.
  4. Akihiro Nakasjima et al., IEEE Electron Device Letters 32 (2011) 764.
  5. Kenji Nomura et al., Applied Physics Letters 85 (2004) 1993.
  6. SILVACO International, ATHENA, ATLAS, VICTORY Cell and VICTORY Device [Online]. www.silvaco.com/products


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