Self-Heating effect Simulation of GaN HFET Devices
- 4H-SiC and Sapphire Substrate Comparison


I. Introduction

GaN-based Hetero-Field Effect Transistors have been investigated in high power and high frequency electronics devices. However, such improved performance is still subject to influence of surface and buffer traps. The role and dynamics of traps and their effect on the GaN HFET have already been investigated [1]. In addition to the formation of the 2DEG, an adequate numerical model of device charge control implies proper modulation of the 2DEG in ATLAS [2].

In this paper, in order to understand and control the self-heating effect, the device was simulated including this effect on a 4H-SiC and a Sapphire substrate, and Id-Vd characteristics were compared using the ATLAS 2D device simulator.


II. Device Structure and Simulation Models

The physical devices simulated in this paper are Al0.25Ga0.85N-GaN HFET on either semi-insulating 4H-SiC or Sapphire substrates. The structure consists of a 0.5um AlN layer and undoped 3um GaN, and 3 AlGaN layers, which includes 3nm undoped AlGaN and 10nm doped 1e18 n+AlGaN and 10nm undoped AlGaN as shown Figure 1.

Figure 1. Schematic cross section of the simulated AlGaN/GaN HFET.


The Gate, Source and Drain electrode are on the top surface. The space of the Source-Gate and Drain-Gate are 2.0um and 4.0um respectively.

The strain-induced piezoelectric polarization and the spontaneous polarization of the interface of AlGaN/GaN are taken into account in ATLAS.

The 2DEG was adjusted to 8e12cm-2 using the polarization calculation and scaling parameter.

The trap density and cross sections used in in Nitride materials have been chosen according to experimental observations and theoretical calculation [3]. Bulk traps with a trap density of 1.0e17cm-3 a cross section of 1.0e-15 cm-2 and energy position of 2eV below the conduction band have been used.

The drift-diffusion transport model is used for this simulation with the Farahmand Modified Caughey Thomas (FMCT) mobility for low field[4], and the high field dependent mobility model is based on fitted Monte Carlo data for bulk nitride [5].


III. Self-Heating Effects

Self-heating is a local increase of crystal temperature due to dissipated Joule electric power. Figure 2 shows the current-voltage (Id-Vg) and transconductance (gm) with thermodynamics model due to the substrate materials, 4H-SiC and Sapphire. Figure 3 shows the lattice temperature distribution on the 4H-SiC substrate with a hot spot visible at the drain-side gate edge. Table I shows the material parameters of the thermal conductivity of the GaN based HFETs devices.

Figure 2. Id-Vg and gm curve due to the substrate materials.


Figure 3. Lattice Temperature distribution on 4H-SiC substrate at Vd=5V Vg=0V



Table I. Thermal conductivity of materials (Unit : W/cmK).



To estimate the full thermal characteristics, it is important to calibrate the lumped external thermal resistance, Rth in K/Wcm2. In this simulation, the substrate layer was chosen as 100um thick which fully considered the vertical thermal spreading of the substrate, the Rth was chosen as 1.25e-4. K/Wcm2.

Figure 4 shows the IdVd characteristics versus gate bias. Fig.4 (a) is on the 4H-SiC substrate and (b) is on the Sapphire substrate.

(a) on 4H-SiC substrate

(b) on Sapphire substrate

Figure 4. IdVd versus gate bias.

Figure 4 and Figure 5 clearly show that the self-heating effects reduce the electron mobility at the drain-side gate edge, thus degrading the device performance and causing the Negative Differential Conductance (NDC) in the IdVd curves. This decrease can be correlated to the localized hot spot (Fig. 3).

The NDC depends on the substrate material. The Sapphire substrate exhibit stronger NDC compared to 4H-SiC, because the Sapphire thermal conductivity is smaller.

The self-heating effects can be eliminated or significantly reduced by the conventional heat-sink approach in the packed power devices.

Figure 5 shows the peak hot spot temperature versus gate and drain bias. Fig 5. (a) shows that the peak temperature can reach 360 K on the 4H-SiC substrate whereas in Fig 5. (b) the peak temperature rises 472 K on the Sapphire substrate.

(a) on 4H-SiC substrate

(b) on Sapphire substrate

Figure 5. Maximum lattice temperature for different gate bias Vgate=-3.0V, -2.0V, -1.0V 0.0V


IV. Conclusion

The negative differential conductance due to the self-heating effect was demonstrated for different substrate materials. The effect of lattice heating on GaN HFET IV characteristics was investigated using ATLAS.



  1. Simulation Standard, “Trapping Effects in the Transient Response of AlGaN/GaN HEMT Devices”, Vo.17, No.8. Aug. 2007, p.1 - p.8
  2. Simulation Standard, “Simulating the Source of Polarization Charge in AlGaN/GaN HFETs.”, Vo.15, No.8. Aug. 2006, p.1 - p.2
  3. X.H.Wu, et al., “Defect structure of metal-organic chemical vapor deposition-grown epitaxial (0001) GaN/Al2O3”, J.Appl. Phys. 80, 3228 (1996).
  4. ATLAS User’s Manual, 2007.
  5. Farahmand,, “Monte Carlo Simulation of Electron Transport in the III-Nitride Wurtzite Phase Materials System: Binaries and Terniaries”, IEEE TED Vol.48, No.3(Mar. 2001): pp535-542.

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