1. Introduction

Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) Non-Volatile memory structures can be simulated using ATLAS. The basic principle of these devices is the use of a charge trapping Silicon Nitride layer embedded in the oxide layer separating the gate from the channel. This results in an oxide layer between the gate and the Silicon Nitride layer, and another between the Nitride layer and the semiconducting channel (Figure 1). The Silicon Nitride layer can be charged by quantum mechanical tunneling or by hot carrier injection. This results in a shift in the turn-on voltage of the NVM device. The trapped charge can be discharged by quantum mechanical tunneling or by injecting hot carriers of the opposite polarity, thereby erasing the threshold Voltage shift.[1] [2]


2. Models

ATLAS models the trap states in the Nitride as being either acceptor-like (for storing electrons) or donor-like (for storing holes), at a single discrete energy level below the Nitride conduction band (acceptor-like) or above the valence band (donor-like). The number of available trap states is assumed to be spatially uniform, and the trap state occupancy is dynamically determined from the following differential equations:

where nt and pt are the trapped electron and hole concentrations, SIGMAT.N and SIGMAT.P are the capture cross-sections for electrons and holes respectively, and NT.N and NT.P are the maximum possible concentrations of trapped electrons and trapped holes respectively. The carrier thermal velocities are vthn and vthp and also affect how many carriers are captured. The cross-section parameter SIGMAN.P determines the rate of hole capture from the valence band for the acceptor-like traps, and SIGMAN.N the rate of electron capture from the conduction band for the donor-like traps. The rate of emission of trapped carriers are governed by the emission rates en and ep . There are two models for the emission rate, one is that they are fixed (en = 1/TAU.N, ep = 1/TAU.P) and the other is that they are Poole-Frenkel like, increasing with increasing field as shown in the following equation.[3]

where ELEC.DEPTH is the depth of the electron traps below the conduction band, e is the relative dielectric permitivity in the Silicon Nitride and F is the local electric field. The default value of PF.B is 1013 Hz.

In the Silicon Nitride the fully transient current continuity equations are solved, self-consistently along with the equations for the trap occupancy and the Poisson Equation. There is carrier generation at the edges of and within the Nitride, the generated electrons and holes are mobile within the Nitride layer until they are either captured by the traps, recombine across the bandgap, tunnel out of the Nitride or are thermionically emitted. The final distribution of trapped charge depends on the distribution of carrier generation, the parameters of the trap equation and the transient simulation time.

The carrier capture cross-section determines how far injected electrons travel before being trapped in the available Nitride traps. In figure 1 we show the trapped electron profile after charging a SONOS device for a 10-7 s at a gate voltage of 10 Volts. Tunneling current enters the Silicon Nitride at its interface with the tunneling oxide and starts to drift through the Silicon Nitride layer. The electrons are captured at a rate equal to

and so, other factors being the same, depends on the capture cross section SIGMAT.N. We see in figure 1 that the higher capture cross-section means that the electrons are trapped very near to the interface with the tunneling oxide. A cross-section five orders of magnitude smaller allows them to go much further into the Silicon Nitride before being trapped. Those which reach the blocking oxide may tunnel into the contact or be thermionically emitted to the blocking oxide.

Figure 1: Trapped electron profile as a function of capture cross section for two different values of SIGMAT.N (1e-10cm2 and 1e-15cm2.)

In principle, carriers can tunnel directly from the channel into the interior of the Silicon Nitride. This is only possible at gate biases for which the band energy in the Silicon nitride is not less than the corresponding energy in the Silicon channel. This can clearly be seen in figure 2a, the generation rate due to tunneling is mainly in the interior of the Nitride at the lower gate bias. At the higher gate bias value the conduction band edge in the Nitride lies below that in the channel, and this process is not permitted (figure 2b).

Figure 2a: Generation rate due to tunneling as a function of the Gate Voltage.


Figure 2b: Conduction band edge profile as a function of the Gate Voltage.

In this latter case the charging current emerges in the Nitride at its interface with the Tunneling oxide. All tunneling in the SONOS model is direct, and will also behave like Fowler-Nordheim tunneling at large applied electric fields.

The emission rate is a factor in determining the saturation density of trapped charge, and is also a factor in determining erase performance and retention properties of a device. In particular, the Poole-Frenkel option makes the emission rate dependent on the field in the Silicon-Nitride layer. The effect of varying electron trap depth within the Poole-Frenkel model is illustrated in figure 3a, where the device has been charged at 18 V gate bias for 1 second.

Figure 3a: Trapped electron profile as a function of Poole-Frenkel detrapping trap depth parameter.

The shallower trap depth gives a greater electron detrapping rate (emission rate) and so has a smaller density of trapped electrons. The electron recombination rate for the shallower trap near to the tunnel oxide is large because the density has not yet reached its equilibrium level (see figure 3b).

Figure 3b: Electron recombination rate as a function of Poole-Frenkel detrapping trap depth parameter.


The deeper trap has been saturated in this region and has a smaller recombination rate. Nearer to the blocking insulator interface the rate is lower due to the higher detrapping rate and the different electron density. [4] [5]


3. Threshold Voltage Shift Simulation

A charging simulation was performed for a SONOS device with a 2.5 nm thick tunnel oxide, a 5.5 nm thick Nitride layer and a 6.5 nm thick blocking oxide as can be seen in Figure 4. [6] [7]

Figure 4: SONOS Structure.


The essential parameters of the SONOS model are given in Table 1.

Table 1 : Salient parameters of SONOS model.

The shift in Threshold Voltage was obtained as a function of charging time, with Gate Voltage being a parameter. The gate Voltage was ramped linearly over a period of 1 nanosecond. The results are shown in Figure 5. A charging simulation of the Nitride using a Poole Frenkel emission rate (de-trapping rate) model for different trap depths were performed, for a SANOS device with a 4 nm thick tunnel oxide, a 5 nm thick Nitride layer and a 10 nm thick blocking oxide. The difference between SANOS and SONOS model is in the use of Al2O3 as the blocking layer.

Figure 5: Threshold Voltage shift versus programming time for different Gate Voltage.


The essential parameters are given in Table 2.

Table 2: Parameters of SANOS model.

The Threshold voltage shift as a function of time for a charging gate voltage of 18 V was simulated and results are shown in figure 6. The higher the emission rate the smaller the shift in threshold voltage.

Figure 6: Threshold Voltage shift versus programming time for a gate voltage of 18V with different pool frenkel trap depth parameter .


Figure 7 shows saturation of Threshold Voltage versus erase time for a programming condition of Vgate=16V during 0.1s. A complete erase is obtained after 0.1s of erasing time. The result was confirmed using two different threshold voltage extraction (one extracting the gate bias for a drain current of 1e-06A and the other one by extraction the gate bias for the maximum slope of the IdVg curve.

Figure 7: Threshold Voltage shift versus erasing time for a Gate Voltage of 16V.


4. Conclusion

The ATLAS device simulator was used to model the programming and erase behaviour of both SONOS and SANOS Non-Volatile memory devices. The shift in threshold voltages were calculated as functions of the Gate bias and programming time. The physical mechanisms simulated were direct tunneling through the blocking and tunneling oxides, as well as thermionic emission in the case of the SANOS device. Dynamic charge trapping was modeled in the Nitride, including Poole-Frenkel detrapping effects, and also bipolar interactions. Agreement with experimental data demonstrate that ATLAS can be used to model the behaviour of SONOS-like devices, and particularly the effect of the gate stack structure on the charging and erase performance.



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