Double-Gate Tunnel FET With High- Gate Dielectric

Kathy Boucart and Adrian Mihai Ionescu, Member, IEEECopyright © 2007 IEEE. Reprinted from IEEE Transactions on Electron Devices, VOL 54, NO 7, July 2007.


Abstract—In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG Tunnel FET), for which the simulations show significant improvements compared with single-gate devices using an SiO2 gate dielectric. For the first time, DG Tunnel FET devices, which are using a high- gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA for a gate voltage of 1.8 V, an OFF-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2-D nature of Tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, Tunnel FETs with a high- gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 x 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the Tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

Index Terms—Band-to-band tunneling, double gate (DG), gated p-i-n diode, high- dielectric, subthreshold swing, tunnel fieldeffect transistor (FET).


Manuscript received September 13, 2006; revised February 26, 2007. The review of this paper was arranged by Editor C.-Y. Lu.

The authors are with the Swiss Federal Institute of Technology, 1015 Lausanne, Switzerland (e-mail:

Digital Object Identifier 10.1109/TED.2007.899389


AS MOSFETs continue to get smaller and run into fundamental performance limitations, there is a renewed interest in exploring devices that use tunneling for their ON-current [1]–[14]. In particular, there is a focus on devices which act as field-effect transistors (FETs), where a change of gate voltage turns the current ON and OFF, but which use band-to-band tunneling in their ON-state, as well as in the transition between the OFF- and ON-states. These devices have the potential for extremely low OFF-current, and present the possibility to lower the subthreshold swing beyond the 60-mV/dec limit of conventional MOSFETs. Therefore, they seem well adapted to be candidates for an ultimately scaled quasi-ideal switch.

One such reported device is the Tunnel FET that incorporates a delta-layer of SiGe at the edge of the p+ region, in order to reduce the barrier width and, thereby, improve the subthreshold swing and ON-current [10], [11]. Another is the carbonnanotube FET, which uses two independently controlled gates to change the energy bands in the channel [7].

In most of the literature published so far, the experimentally shown ON-currents are unacceptably low for a technology that would like to replace the conventional MOSFET (hereafter, simply referred to as the MOSFET). While OFF-currents are in the range of femtoamperes [7] or picoamperes [8], [9], ON-currents for applied drain and gate voltages of 2 V are still limited to the nanoamperes range [8], [9]. Furthermore, in order to have a CMOS-compatible technology, voltages should be limited even more, to about 1.2 V. While one publication shows ON-currents up to 0.5 mA/µm [13], these devices seem to be hybrid devices rather than pure Tunnel FETs, since their subthreshold slope is constant rather than Vg-dependent.

Looking at the 2005 ITRS [15], the Tunnel FET technology fits best into the Low Standby Power (LSTP) category. For the 50-nm node, an ON-current of 0.612 mA is required with an OFF-current of 10 pA. New Tunnel FET designs will be needed, in order to attain this Ion without sacrificing Ioff. The design we present here, a double-gate (DG) device with a high- gate dielectric, is a way of achieving similar improvements (with an ON-current of 0.23 mA, lower than the ITRS requirement, but an off-current significantly reduced compared to a conventional MOSFET), while taking advantage of the reduced subthreshold swing possible with this sort of tunneling device. It is important to notice that the results presented here (notably, the ON-current) are not identical with those shown in our earlier report [21], due to a change in the band-to-band tunneling model. The new results, however, qualitatively confirm all initial findings and orders of magnitude (this will be discussed in detail in Section IV).

For reasons of cost and compatibility with already-existing fabrication technology, a process that uses standard CMOS fabrication steps and batch (rather than wafer-by-wafer) processing is preferable. The devices simulated here have been designed to be compatible with this type of processing, to make integration with CMOS possible and to keep costs low. The materials can be deposited with bulk-deposition methods, such as chemical vapor deposition (CVD), rather than expensive techniques, such as molecular beam epitaxy (MBE).

This paper explains the structure of a Tunnel FET and how it functions (in Section II), and discusses subthreshold slope for both MOSFETs and Tunnel FETs (in Section III). Section IV shows how the novel DG design, with an optimized silicon body thickness and a high- gate dielectric, results in improved device characteristics in terms of current and subthreshold swing, and discusses the 2-D nature of this device. The effects of temperature are also mentioned.



The investigated device structure is a lateral n-type Tunnel FET in a thin silicon layer, isolated from the substrate by a dielectric layer. The basic design is a gated p-i-n diode. The tunneling takes place in this device between the intrinsic and p+ regions. Schematics of two of the devices simulated are shown in Figure 1; here, our discussions will primarily focus on the DG device. To operate these devices, the p-i-n diode is reversebiased —in our simulations, the source is grounded, and a positive voltage is applied to the drain—and a voltage is applied to the gate(s). Without a gate voltage, the width of the energy barrier between the intrinsic region and the p+ region is much wider than 10 nm (the approximate minimum for significant tunneling probability), and the device is in the OFF-state, as shown in the cross section of the device in Figure 2(a). As the positive gate voltage increases, the bands in the intrinsic region are pushed down in energy, narrowing the tunneling barrier and allowing tunneling current to flow, as shown in Figure 2(b).

Figure 1. Simulated Tunnel n-FETs. (a) Single-gate. (b) DG. SiO2 and high- gate dielectrics were studied. tdielectric = 3 nm (physical) and Lintrinsic = 50 nm. Drain doping (n+) = 5 °— 1018 atoms/cm3 and source doping (p+) = 1020 atoms/cm3.


Figure 2. Device structure corresponds to Fig. 1. (a) Schematic of energy-band diagram of the OFF-state of the Tunnel FET. Vd = 1 V and Vg = 0 V. In this state, the only current is p-i-n diode leakage current. (b) Schematic of energy-band diagram of the ON-state of the Tunnel FET. In this state, the energy barrier is thin enough that electrons can tunnel from the valance band of the p+ region to the conduction band of the intrinsic region. Vd = 1 V and Vg = 1.8 V.


In order to be consistent with MOSFET technology, the names of the device terminals are chosen such that voltages are applied in a similar way for Tunnel FET operation. Since a reverse bias is needed across the p-i-n structure in order to create tunneling and since an NMOS operates when positive voltages are applied to the drain and gate, the n-region is referred to as the drain and the p+ region as the source.

Doping has been optimized in order to create the maximum ON-current, while keeping OFF-current low. As discussed in the study in [8], it is desirable to have a high source doping (around 1020 atoms/cm3 or even higher) but a lower drain doping. For these simulations, the doping levels were 1 x 1020, 1 x 1017, and 5 x 1018 atoms/cm3 for the source, intrinsic, and drain regions, respectively.

The work function chosen for the gate contact is 4.5 eV, corresponding to a metal gate stack. This could correspond to a stack comprised of tungsten (W) and titanium nitride (TiN) [16].



The subthreshold swing of a device is defined as the change in gate voltage which must be applied in order to create a one decade increase in the output current or

The subthreshold swing of a MOSFET is limited by the diffusion current physics of the device in weak inversion, such that the minimum possible swing in an ideal device is

which is about 60 mV/dec at room temperature (300 K).

A Tunnel FET, on the other hand, does not experience the same physical limitation, because the current mechanism relies on the tunneling-barrier width rather than the formation of an inversion channel. Starting from Hurkx’s band-to-band tunneling model [17, eq. (12)], as used in Silvaco ATLAS [18], the subthreshold slope for a Tunnel FET can be expressed in terms of the gate voltage as

where the constant is determined by device dimensions and material parameters. Equation (3) shows that, in Tunnel FETs, the subthreshold slope is highly dependent on the gate voltage, and one should distinguish between the point and the average slopes (the latter being the more important for switch performance). This is an important remark for future benchmarking of new abrupt switch solutions, for which most reports currently point to the optimization of the point slope only.

The benefits of a DG Tunnel FET over a DG MOSFET is shown in Figure 3, which compares the Id–Vg characteristics of an optimized asymmetrical DG MOSFET from [19] with those of a simulated DG Tunnel FET, being proposed for the first time in this paper. The two devices have the same dimensions for dielectric thickness (3 nm), channel length (i-region length in the Tunnel FET, equal to 50 nm), and body thickness (10 nm). The optimized DG Tunnel FET uses a high- gate dielectric with a dielectric constant of 29, as will be discussed later. It is important to notice the difference between the subthreshold regions in these two types of devices. A MOSFET has a constant slope between the OFF-state and threshold. A Tunnel FET, however, demonstrates a slope that is steeper (smaller swing) closer to the OFF-state and less steep closer to threshold and varies as a function of the gate voltage. Since the threshold voltage of a Tunnel FET cannot be extracted using certain standard MOSFET techniques, in this paper, we use the constant-current method, with a threshold current of 10-7 A/µm.

Figure 3. Comparison of simulated DG-Tunnel-FET characteristics with those of an optimized asymmetrical DG MOSFET (from [13]). While the subthreshold slope is constant for a MOSFET in the subthreshold region, it is a function of Vg for a Tunnel FET. Both devices have L = 50 nm, tbody = 5 nm, and tdielectric = 3 nm. Vd = 1 V. Inset: Extraction of the average slope, and the point at which the point slope is measured.


It is clear that the swing for the Tunnel FET in Figure 3 is lower than that of the MOSFET, whether we look at the point slope or the average slope. The point value of S is defined as the minimum swing value at any point on the Id–Vg curve. The average S value is calculated between the voltage at which the current begins to increase with increasing gate voltage, and the threshold voltage. These two values are different because S is a function of Vg. Their extraction is shown in the inset of Figure 3.

A key issue in future DG Tunnel FETs is the simultaneous optimization of Ion–Ioff and subthreshold swing. A basic analytical formulation of the tunneling probability T(E), for ultrathin films and gate oxides, has been derived in the study in [20] and shows that

where m* is the effective carrier mass, Eg is the bandgap, is the energy range over which tunneling can take place, and tox, tSi, eox, and eSi are the oxide and silicon film thickness and dielectric constants, respectively. Equation (4) suggests that high-£e dielectrics would favor an increased tunneling rate. This comes from the improved electrical coupling between the gate and the tunneling junction due to the increased gate capacitance. In contrast with a MOSFET, the current has an exponential dependence on the square root of the gate capacitance rather than a linear one. Based on this observation, we focus our device optimization on DG Tunnel FETs with high- gate dielectrics rather than on the engineering of the material bandgap (as in previous approaches [10], [11] that proposed Tunnel FETs with SiGe).



A. Simulation Parameters
All simulations were done in Silvaco ATLAS, version 5.11.24.C, which uses a nonlocal Hurkx band-to-band tunneling model [18]. This version of Atlas shows better physical consistency over the version used in a previous publication [21], which used a local band-to-band tunneling (BTB) model. The previously used local model calculates a generation rate at each mesh node from the magnitude of the electric field. In contrast, the currently used nonlocal model works by calculating the tunneling probability from the energy-band diagrams across the device. The simulations use a very fine mesh across the region where the tunneling takes place, from which energyband profiles and the energies for which band-to-band tunneling is permitted, are determined. The positions for the start and end of tunneling are found for each energy and are used to calculate the current in that energy range. ATLAS uses a two-band approximation for the evanescent wavevector and a carefully applied Wentzel–Kramer–Brillouin method.

Gate leakage was neglected in these simulations and can be expected to limit the OFF-current in fabricated Tunnel FETs. Bandgap narrowing was enabled.


B. Double Gate (DG)
In an integrated DG-CMOS/DG-Tunnel-FET process, the Tunnel FETs will benefit from the added gate, such that the current will be at least doubled. In this way, the ON-current is boosted, while the OFF-current, still in the femtoamperes or picoamperes range, increases by the same factor but remains extremely low. It is worth noting that, for ultrathin silicon-on-insulator (SOI) MOSFETs, some reports suggest that this improvement can be even higher when volume inversion takes place [22].


C. High- Gate Dielectric
An even higher ON-current and decreased subthreshold swing can be obtained by the careful choice of a gate dielectric. As shown in Figure 4(a), current increases as the gate dielectric constant increases. Here, Si3N4 and two high- dielectrics, HfO2 and ZrO2, are compared to SiO2, all with a physical thickness of 3 nm. The high- materials have dielectric constants of 21 and 29, respectively. The reduced effective oxide thickness provided by these dielectrics offers a solution to the low-ON-current problem experienced by some existing Tunnel FETs at CMOS-compatible voltages. The OFF-current is less than 1 fA.

Figure 4. (a) DG-Tunnel-FET characteristics for various gate dielectrics. = 3.9 corresponds to SiO2, = 7.5 to Si3N4, = 21 to HfO2, and = 29 to ZrO2. Lintrinsic = 50 nm, tdielectric = 3 nm, and tSi = 10 nm. Vd = 1 V. (b) Characteristics of a simplified single-gate NMOSFET for various gate dielectrics. Junctions were ideally abrupt, as for the Tunnel FET, with source and drain doped to 1020 and the p-type body doped to 1017, L = 50 nm, tdielectric = 3 nm, and tSi = 5 nm. Vd = 1 V.

Interestingly, the ON-current does not increase merely proportionally to the increase in the gate capacitance, as it would for a MOSFET. A simplified MOSFET 2-D structure has been designed for numerical simulation in order to show the difference between the two [Figure 4(b)]. For Tunnel FETs, as we saw in (4), the improved coupling between the gate and the tunneling barrier has an exponential effect rather than a linear one. The ON-current of a Tunnel FET depends on the width of the energy barrier between the intrinsic and p+ regions, and the current increases exponentially with a reduction in this barrier width. Figure 5(a) shows the dependence of the energy-barrier width on the gate voltage for the gate-dielectric constants studied. The barrier width was extracted from the simulated band diagrams at a distance of 2.5 nm from the dielectric surface, with 1 V applied to the drain and the source grounded. Figure 5(b) shows the exponential dependence of the simulated tunneling current on the barrier width. Figure 6 shows the normalized Id–Vg characteristics for different gate dielectrics, with each drain–current divided by the gate-dielectric constant of that device. From this figure, it is clear that the improvement in current cannot be simply attributed to a proportional increase of the gate capacitance with the gate-dielectric constant.

Figure 5. (a)Width of energy barrier, for band-to-band tunneling, versus Vg, for different values of the gate-dielectric constant. (b) Drain current versus energybarrier width for different values of the gate-dielectric constant.


Figure 6. DG Tunnel FET characteristics, normalized for each gate-dielectric constant (drain current/gate-dielectric constant). Vd = 1 V. The increase in drain current is not linearly proportional to the increase in gate capacitance as it would be for MOSFET. Device corresponds to Fig. 1.



In addition to improved Ion, both the point and average subthreshold swing improve as the result of the better gate coupling given by a high- dielectric. By raising the ON-portion of the Id–Vg curve [see Figure 4(a)], we effectively “uncover” a steeper part of the curve in the subthreshold, decreasing the point swing. The average swing is also much improved with a high- dielectric, since the threshold voltage falls on a steeper part of the curve. In contrast, the MOSFET swing hits the 60-mV/dec limit [Figure 4(b)] and cannot improve further.

Figure 7 shows the linear relationship between log(ID) and ox-0.5 , which supports what we expected to see from (4). While high- dielectrics have advantages for device characteristics, when put directly in contact with a silicon channel, they can lead to defects at the semiconductor/dielectric interface. Although Tunnel FETs might be less sensitive to changes in channel mobility than MOSFETs, as will be discussed below, standard CMOS fabrication techniques require an interfacial layer between the high- dielectric and the silicon channel. A Tunnel FET with a more CMOS-compatible dielectric layer has been simulated, and the resulting Id–Vg curve is shown in Figure 8. The simulated device had 1 nm of oxynitride at the silicon surface and 2 nm of ZrO2. It is clear that even with an interfacial layer, the subthreshold slope and ON-current are very much improved over the device with an SiO2 gate dielectric.

Figure 7. log(ID) versus 1/0.5ox; the linearity of the plot is in good agreement with the proposed modeling in (4).


Figure 8. DG-Tunnel-FET characteristics for a structure with 2 nm of a high- ke dielectric ( dielectric = 29) with a 1-nm interfacial layer of oxynitride ( dielectric = 5.7),


High- dielectrics bring additional challenges such as the limitations of soft and hard dielectric breakdown. Depending on the characteristics of fabricated high- dielectric layers, it may be necessary to limit applied gate voltages more than what is reported here. For example, depending on whether the structure of a HfO2 layer is more tetragonal or cubic, the breakdown field could be 3.9 or 6.7 MV/cm, leading to a breakdown voltage of Vg = 1.17 V or 2.01 V [23]. Of course, these voltage numbers would change depending on the high- dielectric thickness and/or the existence of an interfacial layer. Although the current simulations aim to stay within optimistic limits, a reoptimization of the design will be needed once the parameters of fabricated materials are known.


D. Thin-Film Structure
SOI and silicon-on-nothing fabrication technology are two fabrication methods currently used to create DG devices. Both of these techniques are commonly used on thin films, down to several nanometers thick. The thickness of a Tunnel FET influences the shape of its Id–Vg curve, as shown in Figure 9.

Figure 9. DG-Tunnel-FET Id–Vg characteristics for various silicon body thicknesses. Lintrinsic = 50 nm, tdielectric = 3 nm, and dielectric = 29. Vd = 1 V.


Several trends can be seen in this figure. First, OFF-current, which depends on the cross section of the p-i-n structure, slightly decreases as expected with thickness. As the film gets thinner than 10 nm, ON-current starts to drop, possibly due to the reduced cross-sectional area available for current flow. Due to these trends, the ratioIon/Ioff will have a maximum when plotted against silicon-layer thickness. Figure 10 shows that this optimum value occurs when tSi is between 7 and 8 nm, depending on the value chosen for VDD, where Ion is taken at Vg = VDD. The maximum ratio is about 2 x 1011, and as a comparison, the optimized asymmetrical DG MOSFET from [19] has an Ion/Ioff ratio of 106 with Ion taken at Vg = 1.5 V. The order of magnitude of the Ion/Ioff ratio is not dramatically modified by a variation of the film thickness, which would be advantageous if there were variations of body thickness in devices on thin films.

Figure 10. Ratio Ion/Ioff as a function of the silicon layer thickness, for edielectric = 29. A maximum, the optimum point, occurs in the thickness range of 7–8 nm, depending on the value of Vdd used. 1 V was applied to the drain.


Figure 9 also reveals that both the average and point values of subthreshold swing become lower as thickness decreases, as shown in Figure 11. The subthreshold swing also decreases as high- dielectrics are used. While the point swing is lower than the 60-mV/dec limit for MOSFETs for all dielectrics and thicknesses simulated, the average swing is lower than this limit only for a high- dielectric with a constant of 29 (ZrO2) and a silicon body thickness of less than 10 nm. The dependence of swing on the gate voltage up to the threshold voltage is shown in Figure 12, demonstrating that, at low gate voltages, Tunnel FETs have a subthreshold swing under the 60-mV/dec MOSFET limit.

Figure 11. (Left y axis) Point subthreshold swing and (right y axis) average subthreshold swing as a function of silicon layer thickness for different gatedielectric constants. Lintrinsic = 50 nm and tdielectric = 3 nm.


Figure 12. Dependence of the Tunnel FET subthreshold slope on gate voltage for different dielectric constants, from numerical simulation. Each curve goes up to the threshold voltage of that device. L = 50 nm, tdielectric = 3 nm, and tSi = 10 nm.


Clearly, these values of the average swing depend upon our chosen definition for the threshold voltage. A lower constant current value would lower the threshold voltage and, in turn, would advantageously lower the average swing values. It is worth mentioning, however, that qualitatively, all the trends of the curves remain the same.

The relationship between the drain current and the body thickness can be seen in (4): log(ID) is linearly dependent on t-0.5Si . Figure 9 shows that this relation may hold true for devices thicker than about 7 nm, but when the silicon body is too thin, the drain current is limited by the reduced body thickness. Figure 13 shows the extraction of the relationship between log(ID) and t-0.5Si for various values of the gate voltage. This behavior will need to be explored further.


Figure 13. log(ID) versus 1/t0.5Si at different gate voltages; the relationship is approximately linear, in agreement with the proposed modeling of (4).


Similar results are expected for a p-type device, which has opposite doping from an n-type device [21].


E. Two-Dimensional Simulations
All simulations carried out in Silvaco ATLAS were 2-D, and it is informative to look at vertical cross sections of the energy bands of the Tunnel FET, as well as contour plots in two dimensions, in order to understand the functioning of the device. All diagrams are shown for single-gate devices because, with the models currently used, DG devices show identical results, symmetrical for the two halves.

Looking first at the x direction component of the electric field across a device which is ON [Figure 14(a)], we see that the electric field is close to zero nearly everywhere. Between the intrinsic and p+ regions, where the tunneling takes place, we see a high positive field throughout the depth of the device. In the potential contour plot for this same device in the same state [Figure 14(b)], we see that the potential drops abruptly at the tunnel junction, and once again, this holds true for the entire device depth, not just at the surface.


Figure 14. (a) Contour plot of the x-component of the electric field in a singlegate Tunnel FET biased with Vd = 1 V and Vg = 1.8 V, in overdrive, with tdielectric = 3 nm and dielectric = 29. (b) Contour plot of the potential of the same device under the same bias conditions.


In the diagrams of current flowlines, shown at the threshold voltage [Figure 15(a)] and in overdrive [Figure 15(b)], it is clear that the current does not stay close to the gate dielectric as in a MOSFET. As the electrons moves from right to left (source to drain) in the Tunnel FET, they move parallel to the interface through most of the source, then move away from the dielectric interface at about the location of the tunnel junction and, then, attracted by the positive voltage on the gate, flow closer to the interface before spreading back out and passing through the drain parallel to the interface, as they were in the source (electrical contacts are on the sides of the source and drain.)


Figure 15. Current flowlines for the same Tunnel FET as that shown in Fig. 14, with (a) Vg = Vt (obtained using the constant-current technique) and (b) Vg = 1.8 V.


Inspection of some vertical energy-band cross sections can help in understanding this current flow. Figure 16(a) shows the energy bands taken vertically at the junction between the source and intrinsic regions, where the band-to-band tunneling takes place. The energy is lower at the dielectric surface than deep in the body, particularly at high Vg, as can also be noticed in the potential contours where we see that the tunnel junction (the abrupt change in potential) is more in the source near the dielectric and more in the intrinsic region deeper in the body. Therefore, just at this junction, electrons will want to go toward the dielectric, to lower energy. Figure 16(b) shows the energy bands cutting vertically through the very center of the intrinsic region. Here, the bands are nearly flat, and the electrons no longer stay as close to the gate dielectric, as evidenced by the current flowlines.


Figure 16. Cross sections of the energy bands of the same device as that shown in Figs. 14 and 15, taken vertically from the dielectric interface through the body. (a) Cross section at x = 150 nm, just at the junction between the intrinsic and p+ regions, where tunneling takes place. (b) Cross section at x = 125 nm, at the center of the intrinsic region.


The current-flow pattern promises to give an advantage over conventional MOSFETs in terms of the effects of surface roughness on device characteristics. Tunnel FETs should be less affected by variations in mobility due to the current being less confined to the surface under the gate.



F. Temperature
The temperature dependence of silicon Tunnel FETs with an SiO2 gate dielectric has been reported in [9] and [12]. Tunnel FETs with a high- dielectric show the same general trends: the OFF-current, caused by the generation of carriers in a reverse-biased junction, increases with temperature, while the ON-current, coming from band-to-band tunneling, changes only slightly, as shown in Figure 17. The inset of Figure 17 shows that the subthreshold swing of the Tunnel FET for fixed values of Vg is nearly constant as temperature increases, unlike that of a MOSFET, which degrades proportionally to the increase in temperature, as can be seen in (2). Due to the rising OFF-current, the average subthreshold swing of Tunnel FETs will significantly degrade with increasing temperature, but beyond the leakage level, the current characteristics remain nearly unchanged.

Figure 17. Id–Vg characteristics for various temperatures. Vd = 1 V. As temperature increases, Ioff increases, but Ion changes very little. Inset: Slope at specific Vg values, versus temperature in Kelvin. We see that these values of slope are only slightly affected by changes in temperature.


The use of a high- dielectric rather than SiO2 leads to a decrease in the threshold-voltage shift caused by temperature. This is to be expected with the constant-current method of Vt extraction, since with a higher dielectric constant, Vt falls on a steeper part of the Id–Vg curve. While Vt/T is in the range of 1–2 mV/K for Si/SiO2 Tunnel FETs [12] and MOSFETs, we find that Vt/T is 0.2–0.3 mV/K for Tunnel FETs with a gate-dielectric constant of 21.



We proposed and discussed the basic static operation, and studied by simulation the characteristics of a DG Tunnel FET as a better-than-60-mV/dec current switch. The investigated Tunnel FET showed improved characteristics including higher ON current and a lower subthreshold swing, after the proposed design modifications: a double gate, a high- gate dielectric, and an optimized silicon body thickness. The DG and high- dielectric raise ON-current to 0.23 mA at Vg = 1.8 V and provide a corresponding improvement in the average subthreshold swing, as low as 57 mV/dec, and a minimum point swing of 11 mV/dec. An optimum silicon body layer thickness of between 7 and 8 nm was found for the studied device with a gate length of 50 nm, maximizing the ratio Ion/Ioff to 2 x 1011. In addition, the subthreshold swing for fixed values of Vg remains nearly unchanged as temperature increases. The Tunnel FET’s promising behavior makes it a strong candidate to complement or replace MOSFET technology, particularly for LSTP applications.



The authors would like to thank K. Bhuwalka for some enlightening discussions and A. Ferron at Silvaco for the continuing support with ATLASsimulations.


  1. J. Quinn, G. Kawamoto, and B. McCombe, “Subband spectroscopy by surface channel tunneling,” Surf. Sci., vol. 73, pp. 190–196, May 1978.
  2. T. Baba, “Proposal for surface tunnel transistors,” Jpn. J. Appl. Phys., vol. 31, no. 4B, pp. L455–L457, Apr. 1992.
  3. W. Reddick and G. Amaratunga, “Silicon surface tunnel transistor,” Appl. Phys. Lett., vol. 67, no. 4, pp. 494–496, Jul. 1995.
  4. J. Koga and A. Toriumi, “Three-terminal silicon surface junction tunneling device for room temperature operation,” IEEE Electron Device Lett., vol. 20, no. 10, pp. 529–531, Oct. 1999.
  5. W. Hansch, C. Fink, J. Schulze, and I. Eisele, “A vertical MOS-gated Esaki tunneling transistor in silicon,” Thin Solid Films, vol. 369, no. 1/2, pp. 387–389, Jul. 2000.
  6. C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, “Lateral interband tunneling transistor in silicon-on-insulator,” Appl. Phys. Lett., vol. 84, no. 10, pp. 1780–1782, Mar. 2004.
  7. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, no. 19, pp. 196805-1–196805-4, Nov. 2004.
  8. P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, “Complementary tunneling transistor for low power application,” Solid State Electron., vol. 48, no. 12, pp. 2281–2286, Dec. 2004.
  9. K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele, “P-channel tunnel field-effect transistors down to sub-50 nm channel lengths,” Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3106–3109, Apr. 2006.
  10. K. Bhuwalka, J. Schulze, and I. Eisele, “Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering,” IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909–917, May 2005.
  11. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical tunnel field-effect transistor with SiGe in the delta p+ layer,” Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073–4078, 2004.
  12. M. Born, K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, and I. Eisele, “Tunnel FET: A CMOS device for high temperature applications,” in Proc. 15th Int. Conf. Microelectron., 2006, pp. 124–127.
  13. T. Nirschl, S. Henzler, J. Fischer,M. Fukle, A. Bargagli-Stoffi, M. Sterkel, J. Sedlmeir, C. Weber, R. Heinrich, U. Schaper, J. Einfeld, R. Neubert, U. Feklmann, K. Stahrenberg, E. Ruderer, G. Georgakos. R. Kakoschke, W. Hansch, and D. Schmitt-Landsiedel, “Scaling properties of the tunneling field effect transistor (TFET): Device and circuit,” Solid State Electron., vol. 50, no. 1, pp. 44–51, Jan. 2006.
  14. Q. Zhang, W. Zhao, and A. Seabaugh, “Analytic expression and approach for low subthreshold-swing tunnel transistors,” in Proc. DRC, Santa Barbara, CA, Jun. 20–22, 2005, pp. 161–162.
  15. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2005. [Online]. Available: http://
  16. B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J. A. Chroboczek, P. Masson, R. Truche, A. M. Papon, F. Martin, J. F. Damlencourt, S. Maitrejean,M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, “75 nm damascene metal gate and high- integration for advanced CMOS devices,” in IEDM Tech. Dig., Dec. 8–10, 2002, pp. 355–358.
  17. G. Hurkx, D. Klaassen, and M. Knuvers, “A new recombination model for device simulation including tunneling,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331–338, Feb. 1992.
  18. ATLAS User’s Manual, Silvaco Int., Santa Clara, CA, May 26, 2006.
  19. K. Kim and J. Fossum, “Double-gate CMOS: Symmetrical- versus asymmetrical-gate devices,” IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 294–299, Feb. 2001.
  20. J. Knoch and J. Appenzeller, “A novel concept for field-effect transistors—The tunneling carbon nanotube FET,” in Proc. 63rd DRC, Jun. 20–22, 2005, vol. 1, pp. 153–156.
  21. K. Boucart and A. M. Ionescu, “Double gate tunnel FET with ultrathin silicon body and high- gate dielectric,” in Proc. ESSDERC, 2006, pp. 383–386.
  22. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410–412, Sep. 1987.
  23. J. McPherson, J.-Y. Kim, A. Shanware, and H. Mogul, “Thermochemical description of dielectric breakdown in high dielectric constant materials,” Appl. Phys. Lett., vol. 82, no. 13, pp. 2121–2123, Mar. 2003.


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