Optimization of 2D and 3D MIM Capacitors Design
for High Frequency Applications using QUEST



The Metal-Insulator-Metal capacitor is a key passive component in Radio Frequency (RF) and analog integrated circuits. MIM capacitors have attracted great attention because of their high capacitance density that supplies small area, increases circuit density, and further reduces the fabrication cost. The objective for this device is to reduce parasitics (resistance, inductance) and thus increase the quality factor. An article presented in ESSDERC 2005 (also reported in Simulation Standard, November 2005) is devoted to MIM capacitor performance optimization and also compares 2D MIM capacitors measurements and QUEST simulations [1]. The goal of this paper was to present a methodology to analyze and predict MIM capacitors performances using QUEST. Thanks to QUEST simulations, impact of new high-k dielectrics and new designs on MIM capacitor electrical performances were predicted for future generations of RF integrated circuits. It was especially highlighted that new design was required to reduce the parasitic serial inductance in order to enable high-performance MIM capacitor integration for high-frequency applications. We want to remember here that QUEST is based on a 3D field solver elaborated by SIMUCAD in collaboration with CEA-LETI [2][3]. It uses an original formulation of the Quasi-Static Maxwell equations where the problem is separated in two parts, an impedance and a capacitance part. We propose in this new article to focus our attention on how electrical MIM capacitor parameters (R,L,C) are extracted and how automatically, layout generation is performed, for subsequent electrical MIM capacitor parameters model generation and analysis. The last part of this article is devoted to study capacitance density increase through 3D high-density architectures. We will demonstrate QUEST capabilities to simulate 3D MIM capacitor.


2. MIM electrical parameters extraction
The damascene capacitors under study are illustrated in Figure 1. One structure is shown as examples. The area (3 300 µm) leads to a capacitance of 6.6 pF.


Figure 1: Top views and 3D MIM capacitor structure. W1 = 66 µm, L1 = 66 µm.


All MIM capacitors are integrated between M5 and M6 levels as shown in Figure 2.

Figure 2: 3D view of MIM capacitor, where TM6 ~ 800 nm, TM5 ~ 300 nm, and TMIM ~ 400 nm.


The MIM capacitor is characterized by the serial complex impedance ZS. QUEST simulates scattering parameters and Z0 impedance of measurement references planes (P1 and P2) are used to calculate the B element of the transfer matrix ABCD. Then, ZS MIM capacitor impedance is directly extracted by the following formula:

In order to have access to MIM capacitor electrical parameters in a high-frequency regime, an equivalent circuit model is established as shown in Figure 3. The elements C and Rp figure the basic model for the capacitor, whereas additional series Rs and Ls represent the parasitic resistance and inductance due to the specific electrode design [1].


Figure. 3: Equivalent electrical model of MIM capacitors extracted at a high-frequency regime. Measurement plane references are at the capacitor borders.

Due to high fluctuation of the Rp parameter during extraction we reduce the equivalent electrical model to a simple RLC model. The impedance of this model was calculated and its real and imaginary parts were clearly identified. Coupled with the ZS MIM capacitor impedance, each element of the equivalent circuit model is extracted using the entire frequency range. The build-in QUEST optimizer, coupled with the build-in QUEST script analysis [2] was used (Figures 4 and 5) to determine each of the 3 parameters, C, Rs and Ls, that appears in the equivalent circuit model.

Figure 4: Build-in QUEST script from which the optimization is started.


Figure 5: Optimizer showing the equation used for Zs imaginary part (B_I) and the extracted parameters C and L.


Since the extraction procedure is in place, we can now study different designs and the impact on MIM capacitors performances. For that purpose, the script language of Expert layout editor from SIMUCAD was used to create a generic parameterized MIM capacitor gds2 as shown in Figure 6 and Figure 7. Width and Length were defined as layout variables.

Figure 6: EXPERT lisa script used to generate MIM capacitor with Width and Length as parameters.


Figure 7. Resulting gds2 layout with W=6 and L=1 in this case.


We have automatically generated 4 different layouts and ran these layouts in parallel on a multi-cpu machine as QUEST allowed. The different values of W and L are shown in the Table 1. W and L have arbitrary unit since W=1 and L=1 correspond to a “square” cell.

Width W (a, u)
Length L (a, u)

Table 1.

Note also that we have simultaneously made variation of process parameter like the inter-metal dielectric thickness (4 different values) finally leading to 16 simulations. Results are shown in Figure 8.

Figure 8: Simulation results. W, L and DIELEC1_THICK are variables C1 and L1 are MIM capacitor extracted electrical parameters.


Analysis of simulated results shows that Inductance parameter is dependent of the capacitor width whereas it is not the case for the capacitance parameter (Figure 9). The best MIM capacitor design is the one minimizing the capacitor width since the parasitic inductance value is low.

Figure 9: Extracted Capacitance (C) and inductance (L) as a function of capacitor width with inter-metal dielectric thickness as parameter.


We can also analyze the electrical MIM capacitor parameters as a function of process parameters as shown in Figure 10. We observe a non-linear behavior of the capacitance parameter as a function of inter-metal dielectric thickness. This could be explained by a 3D effect originating from the fact that top and bottom electrodes of the MIM capacitor is not perfectly aligned.

Figure 10: Extracted Capacitance (C) as a function of capacitor inter-metal dielectric thickness for W=2 and L=2.


This modelization approach represents a very good solution to optimize electrical performances of MIM capacitors. Indeed, based on the model, the user can define a target value for C and/or L and get the corresponding W, L and inter-metal dielectric thickness.


3. 3D MIM Capacitor Simulation.

The objective of integrating 3D MIM capacitor in actual design is to increase and control the capacitance value without increasing silicon area. The challenge is even more interesting and fit perfectly with QUEST capabilities since the parameters to optimize are not only the design but also the process (dielectric permittivity, electrode resistivity, material thickness).


3.1 Comparison with Measurements
3D MIM capacitors fabricated by ST Crolles, measured by LAHC University were simulated by QUEST. The type of MIM capacitor is shown in Figure 11.

Figure 11: Schematic 2D view of measured and simulated MIM capacitor.


Different lines width, spacing between lines and length (third dimension of the 2D view in Figure 11) were measured and simulated corresponding to 3 different capacitance values: 2.25pF, 4.5pF and 9pF respectively named H, F and G in Figure 12. Simulations shown in Figure 12 are in good agreement with measurements (not shown).

Figure 12: Simulated Imaginary part of the Impedance of the MIM capacitor.


Capacitance parameter extraction was done, from Figure 12, using the methodology describe in part 2 of this article. Comparison was made with measurements and theoretical values and shown in Table 2.

C theoritical 2.25pF
C measured
C simulated

Table 2.


3.2 Process Optimization
An example of 3D MIM capacitor process optimization is described in the following. In the MIM capacitor the reference electrode was set below the MIM itself in the first metal layer as shown in Figure 13.

Figure 13: Schematic (2D) and 3D MIM capacitance with the reference electrode set below the MIM.


Simulations were performed using SiO2 as inter-metal dielectric. Like for 2D MIM capacitor electrical MIM capacitor parameters like C, L and R can be modeled as a function of process parameters. We have made variation of MIM metal thickness shown in Figure 14 (in blue).

Figure 14: Schematic (2D) MIM capacitance with the metal thickness (BLUE) that has been varied.


Capacitance (C), Inductance (L) and resistance (R) parameters are modeled as a function of metal thickness and are shown in Figure 15, Figure 16 and Figure 17.

Figure 15: Extracted Capacitance (C) as a function of metal thickness.


Figure 16: Extracted Inductance (L) as a function of metal thickness


Figure 17: Extracted Resistance (R) as a function of metal thickness.


The analysis of the results indicates that:

  1. The increase of the capacitance by 50%, when the metal thickness increase from 0.2um to 0.8um, induces an increase of 25% for the inductance.
  2. The resistance increases with frequency which is the result of the skin effect
  3. The increase of the capacitance by 50%, when the metal thickness increase from 0.2um to 0.8um, does not impact the resistance value.

As a consequence the designer can increase the metal thickness and thus increase MIM capacitor performance without increasing parasitic inductance and resistance.



Accuracy and efficiency of QUEST for 2D and 3D MIM capacitor simulation is established. High-frequency behavior of MIM capacitors was simulated to investigate electrical performances as a function of design and material parameters. Based on these results, optimized process parameters and new design will increase the capacitance value without increasing too much parasitic inductance and resistance values in order to enable high-performance MIM capacitor integration for high-frequency applications.



We want to acknowledge ST Crolles France and LAHC laboratory from Savoie University France for their high quality support and contribution.



  1. J.Piquet, O.Cueto, F.Charlet, M.Thomas, C.Bermond A.Farcy, J. Torres, B.Fléchet “Simulation and characterization of High-Frequency Performances of Advanced MIM Capacitors” ESSDERC proceeding pp 497-500 2005
  2. S.Putot et al. “A fast and accurate computation of interconnect capacitances” IEDM99, pp 893-897.
  3. F.Charlet et al. . Extraction of 3D interconnect impedances using edge elements without gauge condition. SISPAD 2002.
  4. QUEST: Inductance Optimization Using, 3D Field Solver based on DoE Approach, Simulation Standard Volume 16, Number 2, February 2006.

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