A Semi-Analytical Model for the Subthreshold Behavior of FinFLASH Structures

L. Perniola, J. Razafindramora, P. Scheiblin, F. Daug´e, C. Jahan, B. De Salvo, G. Reimbold, F. Boulanger
17, Rue des Martyrs, F - 38054, Grenoble, France, luca.perniola@cea.fr
G. Ghibaudo
3, Parvis Louis N´eel, BP 257, 38016 Grenoble Cedex 1


Abstract—In this paper we present an original semi-analytical model for the subthreshold electrical behavior of complex 3D structures as the SOI FinFLASH devices. This physically-based model, which does not need any fitting parameter, solves the Poisson equation for a fin covered by trapped charges in the active dielectrics. The analytical results are compared with fully 3D numerical simulations and a good agreement is obtained down to fins with very small feature sizes (order of tens of nm). This model can be efficiently used to gain information on important cell electrical behaviors as the threshold voltage shift Vth and the subthreshold slope factor S.



The FinFLASH device in trigate (W ≈ H, see Fig. 1) or double-gate (H _ W) configuration is currently investigated as one of the most promising solutions to replace conventional planar FLASH structures beyond the 32 nm technology node[1]-[2]. The main advantages of the FinFLASH device are its compact layout, moreover fully compatible with future generations of multi-gate CMOS, and its excellent electrical performance due to the enhanced coupling between the gate and the active channel. In this frame, it is today of utmost importance to provide a simple approach which allows us to describe the most important electrical parameters of the memory operation without applying time consuming 3D numerical simulations.

Fig 1. Plot of the modeled SOI FinFLASH structure. Relevant features used both in the model and in 3D TCAD simulations are highlighted.


In this paper we present 3D fully numerical simulations of FinFLASH devices (Fig. 2a) to substantiate our simpler analytical approach for the comprehension of the electrical behavior of such complex structures (see Fig. 2b). The comparison will be focused on the subthreshold electrostatics (Fig. 3) as well as on the electron transport (see Fig. 4 and Fig. 5). In the end we will analyze the limit of validity of our model in terms of doping level (see Fig. 7) and minimum feature sizes of the fin.


Model for Electrostatics and Transport

The bases of the physics of our model are herewith detailed. The model solves the potential of a FinFLASH device, FFLASH, as the sum of the potential of a FinFET fresh device, ZFFET, plus the potential due to the trapped charges around the fin Zq-tot. The superposition principle can be used if the impact of mobile charges is neglected, therefore the device is operated in the subthreshold region.

Fig. 2. (a) FinFLASH structure employed in 3D simulations. Only half a structure is represented and simulated because of symmetry considerations with respect to a longitudinal plane at the middle of the device. The gate stack is transparent to let appear the floating gate around the fin. (b) FinFLASH schematic employed for the analytical model to solve the electrostatics under weak inversion. Among the boundary conditions, it should be noted the Neumann condition (dV/dz = 0) at the bottom side due to the presence of the thick BOX. Source and drain equivalent metallic plates are transparent to let appear the domain of analysis. The point charges are afterwards integrated to obtain the uniformly charged floating gate.


The model starts from the solution of the Laplace equation for FFET in the FinFET space domain Ω (see Fig. 2b) with mixed boundary condition on G [3]. FFET, indeed, is the potential distribution of a non-doped fin where mobile charges are neglected and the control oxide region is considered as an equivalent silicon region with proper thickness, in order not to treat mathematically the Si/SiO2 interface. The source and drain are treated as perfect metals. Thus FFET solves the following Laplace problem:


where rtg, rrg, rlg are respectively the top, right and left gate potentials, BOX is the potential at the interface silicon/BOX, S and D are respectively the source and drain potentials (see Fig. 2b).

Then we treat separately the impact of a point trapped charge, q. Thus q solves the following Poisson problem:

where si(ox) is the silicon(/oxide) permittivity, is a Dirac Delta function of the coordinates of the charge x0, y0, z0. We originally used the Green’s function method to find an analytical solution to the point charge potential £Zq in a 3D domain [4], where the mixed boundary conditions are properly considered. First the solution to the equivalent homogeneous Dirichlet problem of (2) imposes the research of a Green’s function G, which solves the following:

On the other hand, the Neumann condition at the BOX interface is obtained through the impostion of a fictitious charge of identical sign of the actual charge, mirrored with respect to the plane at z = 0 (look at Fig. 2b).

Thus for a charge q located at (x0, y0, z0), the potential q in (x, y, z) is described by the following Fourier series:

where Weff = W + 2 X (ttun + tcox + tch), Heff = H + X (ttun + tcox + tch) W and H are the width and height of the fin, while ttun, tcox, tch are the tunneling, control and trapping medium oxide thicknesses, as shown in Fig.1.

The impact of each point charge is afterwards integrated in the space domain to obtain the analytical solution for the potential of a uniform distribution of charges around the fin Zq-tot.

Once the potential FLASH of the fin is known, the drain current is calculated through the numerical integration of the electron current density J along the dimensions of the fin, where we assumed a Boltzmann distribution for mobile charges and the Fermi energy level gradient negligible in the xz transversal plane. We obtain:

where K is the Boltzmann constant, T is the lattice temperature, µ is the average electron mobility, ni the intrinsic electron concentration and VDS is the drain-to-source reading voltage.


Numerical Simulations and Discussion

In order to validate our approach, we compared the results obtained by means of the analytical model with a large set of 3D TCAD simulations[5] while varying the features of the memory cell (i.e. dimensions of the fin, tunnel and top oxide thicknesses, amount of trapped charge, etc.). In Fig. 3, we show a comparison of the potential along y for a fresh and a charged cell. We see that we obtain a good agreement between the numerical and the analytical model especially capturing the minimum of the potential, which is the energy barrier peak that has to be overcome by electrons travelling towards the drain. However we note some mismatch approaching the source and drain junction. The potential around these regions is overestimated because the drain and source are represented by metallic plates (see Fig. 2b) which enforce Dirichlet boundary conditions not only along the extremes of the silicon fin, but also along the sides of the oxides up to the gate, where we should have preferably a Neumann boundary condition. This approximation had to be done in order to obtain an analytical solution to our problem, and the limits of validity will be discussed in section IV.

Fig 3. Plot of the fin potential along a longitudinal cut for a fresh and charged device. A fine agreement between the TCAD and model results is apparent even for high drain-to-source voltage reading (W = 40 nm, H = 30 nm).


In Fig. 4 we show a comparison of the electron concentration along z. Indeed, the efficiency of our model in describing both the electrostatics, based on (4), and the transport in 3D structures, based on (5), clearly appears.

Fig. 4. Plot of the electron concentration along the fin height for a fresh and a charged device assuming n = ni exp(q£ZFFLASH/KT), (W = 40 nm, H = 30 nm).


In Fig. 5 we compare the transfer characteristics IDS-VG for two different devices with L = 150 nm and L = 70 nm, and we note that the model fairly agrees with the numerical simulations even for the scaled device.We highlight the fact that we are in the worst reading condition, as we used VDS = 1.5 V, concerning the reliability of the analytical model results.

Fig. 5. Comparison between the transfer characteristics as obtained by TCAD and and by our model for a long and a short FinFLASH device (W = 40 nm, H = 30 nm). We see that for L = 70 nm the model looses accuracy in the Vth value, however still a fine ΔVth and S factor are provided.


In Fig.6 we extended the comparison of Vth and S, the slope factor, to devices with different fin lengths and different aspect ratios, in order to analyze the typical features of a FinFLASH in the double-gate configuration (Fig. 6a) or in a trigate configuration (Fig. 6b). We notice a good agreement in the overall electrical behaviors down to L = 50 - 100 nm.

Fig. 6. Threshold voltage shift and slope factor for (a) a double-gate FinFLASH (H _ W)and for (b) a trigate FinFLASH (H ≈ W). We see that an excellent agreement is found down to L = 100 nm. Below this value the model suffers of excessive impact of drain and source voltages on channel potential.


Limits of Validity

In this section we will analyze the limits of validity posed by the fin doping level and the Dirichlet boundary conditions at source/drain.

Our model is tailored for intrinsic fins, however due to the fact that the electrostatics in such structures is governed more by the geometry of the fin than by its doping level [6], we explored the validity of our approach for doped fins. In Fig. 7 we show the behavior of the programming window with respect to the fin doping level for small and large devices. Even if threshold voltages vary little with respect to fin doping (not shown in the figure), we see that the programming window remains quite constant, thus our model can be used to well predict the threshold voltage shift even for doped fully-depleted devices.

Fig. 7. Comparison between the programming windows obtained by the TCAD and by our model with different fin doping level. Both a large and a small fin device are represented, however the doping level of the fin does not impact much on the device performance at least up to the case of W = L = 60 nm and Nsub = 1018 cm-3, where we deal with a partiallydepleted device.


Concerning the Dirichlet boundary conditions at source and drain, we have to consider that in actual devices source and drain enforce a fixed voltage at the junction with the silicon fin and not over all the area up to the gate contact, as sketched in Fig. 2b. Moreover in the analytical model the oxide should be interpreted mathematically as an equivalent silicon region with suitable enlarged thickness, thus this problem put in serious challenge the model bases. This issue is even more serious for memory devices where the gate stack region is very thick with respect to fin sizes.

As evidenced in Ref. [3], we can highlight a natural decay length Ld of influence of the drain voltage on the fin electrostatics:

This decay length has to be short (i.e. around a half) with respect to the distance between the drain junction and the location of the potential minimum, in order to be sure that the error of the perfect Dirichlet boundary condition at source/drain does not propagate on the drain current calculation. Indeed the minimum of the potential govern the subthreshold current [7], and for resonable value of the reading voltage VDS, it remains around the center of the device length. Therefore we can establish as a safe value for the minimum features of the memory device with thick gate stack, what we obtain from the following criterion:

which means, for instance, a device with features highlighted in Fig. 1 and W=40 nm, H=30 nm, L=90 nm.

The problem of perfect Dirichlet boundary condition at source drain is alleviated by the consideration of epitaxially raised source/drain junctions. As shown in Fig. 2a, the ideal device used for the comparison with TCAD simulation does not have raised source and drain junctions. However in actual devices the source and drain are normally raised in order to diminish access resistance, thus their geometry approaches the assumption of perfect Dirichlet boundary conditions made in our analytical model.



We have presented an original semi-analytical model that efficiently describes important electrical features of complex 3D SOI FinFLASH memory structures operating in weak inversion. The proposed model does not need any fitting parameter and shows a good agreement even for doped fully depleted devices. Indeed, this model could be an effective tool to further investigate the electrical performance (i.e. multibit, multilevel, etc.) of different architectures of FinFLASH cell (i.e. SONOS, nanocrystal-based, etc.), without the need of implementing time consuming numerical simulation.



This work has been done within the framework of the EU FinFLASH project (IST-NMP-FP6 016917).



  1. P. Xuan et al., Tech. Dig. of IEDM, pp. 609-612, 2003.
  2. M. Specht at al., Tech. Dig. of IEDM, pp. 1083-1085, 2004.
  3. G. Pei et al., IEEE Trans. on El. Dev., Vol. 49, No. 8, pp. 1411-1419, 2002.
  4. E. Durand, “ ´ Electrostatique”, Ed. Masson, Vol. II, 1966.
  5. SILVACO-ATLAS User’s Manual, vol. I-II.
  6. J.-P. Colinge, “Silicon-on-insulator technology: materials to VLSI”, Ed. Springer, 3rd Edition, pp. 254-267, 2004.
  7. Y. Taur, T. H. Ning, “Fundamentals of modern VLSI devices”, Ed. Cambridge Univ. Press, 1st Edition, p. 127, 2002.


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