Design Rules and Trends for Dummy Metal Filling Using EXACT, CLEVER and STELLAR


The physical verification is becoming the most complex phase raised by the Deep SubMicron (DSM) technology. More than 50% of the design time is dedicated to the verification. With the shrink of transistors size, the interconnect delay is dominant versus gate delay. Hence the challenge in the DSM technology depends primarily on how to provide accurate characterization of these interconnects. This is especially the case when dummy metals are present.

Floating dummy metals which are inserted to assist planarization of multi-dielectric layers by chemical-mechanical polishing (CMP) process, have created serious problems because of increased interconnect capacitance. We study in this article dummy filling methods to reduce the interconnect capacitance. These techniques include three ways of filling: 1) square 2) parallel lines, and 3) perpendicular lines. For that purpose, we use parameterized layouts allowing, very easily, the variation of dummies geometrical parameters. We then calculate capacitance by using two types of field solver described below. Finally a capacitance model, depending on the dummies geometry is created in order to perform the optimization of the dummies geometry and number.


Parameterized Layout

For this study, we consider a very simple layout consisting of a line over a ground plane surrounded by dummy metals. We wanted to study the impact of dummies geometry and their number on the capacitance between the line and the substrate. For that we use a parameterized layout generator including in our EXACT [1] tool.

The parameterized structure layout generator, within EXACT, provides the user with the capability to define their test structures. This is what was done in this experiment. One combines graphical user interface of EXACT with proprietary scripting language LISA from SILVACO. All the variables are defined within the GUI as shown in Figure 1 as long as a part of the layout. The dummies are defined using the scripting language LISA as shown in Figure 2. It generates one column of dummies at a fixed x-ordinate. In this study, 4 columns have been defined. Therefore this piece of script appended to the layout file saved by the GUI of EXACT.


Figure 1. Layout Variables definition in EXACT GUI.


Figure 2. Dummy generation in LISA language

We have designed the layout so that the dummy density remains constant (the average density of materials oxide and metal is kept constant) since our main interest is to study the impact of dummies geometry on the capacitance rather than the density which is imposed by the CMP process. As the total size of the layout is fixed by the ground plate and constant, and the size of metal line is also fixed, the “constant density” condition is traduced by a constant total surface of dummies (nDlDwD=Cste). That’s why one defines 2 variables: number of dummies nD and their width wD, and so their length lD is a function of both according to the equation above. Depending on the combination (nD, wD), we can see, in Figures 3 and 4, different automatically generated layouts: the “parallel” line configuration, the “perpendicular” and “square” ones.


Figure 3. Typical “parallel” line layout under investigation.



Figure 4. Typical “square” and “perpendicular” lines layouts under investigation.


Another variable, s0 defining the spacing between the line and the nearest neighbour dummies, has been defined. This variable defines the minimum spacing between the line and the dummies (DRC rules) and also serves to avoid very high coupling capacitance between the line and the dummies which may cause troubles when analysing the results.

In this way 64 layouts are generated automatically within EXACT according to Table 1.


Table 1. Layout parameters variations.

Note also that these layouts can be automatically distributed on a multi-cpu machine (one layout per cpu) for capacitance calculation.


Capacitance Calculation

SILVACO parasitic extraction tools keep the same famous in-house trends so-called TCAD driven CAD which means that as a fundamental core a 3D process simulator is coupled to a 3D field solver in order to accurately extract parasitics.

SILVACO has recently released a new interconnect analysis tool to meet the demands of state of the art cell, circuit and chip design. Indeed based on the very deep success of CLEVER [2], SILVACO wanted to provide to customers a tool with the same accuracy but dedicated to bigger layouts. This is the role of STELLAR [3].

Capacitances are calculated from the distribution of charge density on the surfaces of conductors. Classically one can solve partial differential equation on the potential which can be done using finite difference or finite element methods. The normal derivative of the potential on the surfaces gives the charges requested for capacitances calculation. The resultant matrix is sparse but large because the whole dielectrics volume is discretized. A very good 3D tetrahedral mesh is thus needed to solve this problem. Thanks to that, arbitrary conductor shapes and non-homogeneous structure can be handled. This is typically how CLEVER is built.

In STELLAR, a new method [4] called Fictitious Domain is used. Indeed the meshing of a complex 3D domain is avoided by the use of two different meshes: a regular 3D grid on the whole domain and a surface mesh on the conductors. Thanks to this specific grid (volume + surface) the resultant matrix is sparse and a fast solver can be used to solve this system at low memory cost.

STELLAR allows the computation of structures with floating conductors [5]. They are directly taken into account in the differential formulation of the Fictitious Domain method. This original method is particularly efficient when there are many floating conductors as in dummy metal processes. A “floating conductor” is defined to have a constant potential and a global charge equal to zero. As the surface distributions of charge are internal unknowns of the Fictitious Domain Method, these conditions may naturally be introduced in the matrix system.

CLEVER allows also the computation of structures with floating conductors. No special boundary condition is applied on dummy metal as in STELLAR. All capacitances between conductors are computed by CLEVER. Then a post-processing procedure is used to reduce the matrix of capacitances (see appendix A for more details) taking into account dummies.


V- Results and Design Trends

64 layouts describe in Table 1, are simulated using CLEVER. For geometrical analysis purpose we have decided to plot the capacitance between the line and the substrate versus the parameter α:

It means that if α is negative then the dummies exhibit a “perpendicular-like” shape whereas if α is positive, the dummies exhibit a “parallel-like” shape. Finally α equal to zero means that the dummy has a square shape as shown in Figure 5.

Figure 5. Layout having α parameter around zero

Figure 6 shows the results obtained by CLEVER: the capacitance Line-Substrate in fF is plotted depending on α, s0 and nD. The orange horizontal line is the value of the capacitance without dummy. One clearly notes 2 families of curves depending on s0, the smallest value of s0 giving the highest capacitance. Finally the 4 different colors correspond to the different values of nD (see legend).

Figure 6: Capacitance (fF) simulated using CLEVER as a function of the parameter α = (lD/wD)-1, nD and s0.

The 1st interesting point is the distribution of the values. For s0=2.0 µm, the difference between the minimum and maximum of capacitance is only 1% whereas it is 2.5% for s0=0.8 µm. Compared to the value without dummy, the capacitance varies from 1.2% to 5%. The 2nd conclusion is that the capacitance increase is minimum for α positive or close to zero. It means the capacitance is more important when the dummies exhibit a “perpendicular-like” shape. Or reciprocally, the coupling is reduced when the dummies are long and parallel to the line.

EXACT has powerful scripting utilities for manipulating the final capacitance data and variables. Indeed simulated data can be fitted to polynomial expressions using a scripting utilities or statistical analysis like SPAYN. A detailed description of script syntax is available in the EXACT User’s Manual. The idea is to load the capacitance database and make various selections resulting in a table of variables and data that we wish to work with.

We then define an equation that will be used to fit the data by using an optimizer. Usually a quadratic model as shown in Figure 7 is generated allowing the designer to explore, verify and optimize his design.

Figure 7. Quadratic capacitance model done in SPAYN. The capacitance is modeled as a function of nD (number of dummies) and lD (length of the dummies) for s0=2µm

By using this model it is very interesting to notice that the capacitance decreases as the number of dummies increases as can be see in Figure 8.

Figure 8. Capacitance value (fF) as a function of nD (number of dummies) for s0=2µm

We have verified, using the quadratic model that the minimum increase of capacitance exists for “parallel like” shape. Indeed, as shown in Figure 9, a local minimum for capacitance value exist as a function of nD and lD. This minimum corresponds to lD=4.65µm, nD=10 and wD=1.3µm (nDlDwD=Cste=60) thus corresponding to a “parallel like” shape.

Figure 9. Capacitance value (fF) as a function of nD (number of dummies) and lD (dummy length) for s0=2µm


Based on those observations, one can thus estimate that in a real circuit, where signal lines form angles between them (there is obviously not only straight line as in this case under study), the small square shape is probably the most favorable case in order to minimize the increase of parasitic capacitance.


VI- Explanations of the Results

In the previous part different conclusions have been made and some of them are not obvious. For instance the fact the capacitance decreases with the number of dummies and their length. We will try to explain this below.
By using the mathematical description made in Appendix A, it is possible to find a relationship between the capacitance Line/Substrate when all pieces of metal are treated as conductors and when they are all treated as dummies. With some simple assumptions we can write a simple formula:


where indices 1 and 2 stand for Substrate and Line respectively as shown in Figure 10. This means that the capacitance calculated between a line and a substrate is higher when pieces of metal around the line are dummies (constant potential and a global charge equal to zero) as compared to conductors. We will call this effect the dummies effect.

Figure 10: scheme of a Line (2) over Substrate (1) with a conductor (3).


We now want to express Ccond12 (capacitance of a system with conductors) as a function of C∞12 the same capacitance without conductors. In a system with a Line (2) over a Substrate (1) and another conductor (3) far from the Line (see figure 10) we can write this formula:


This equation is not really valid when the spacing between the Line and the conductor (3) is small but the trend is always correct: the capacitance Line/Substrate decreases when a piece of metal is placed near the line. This is the screening effect. The electric field lines between the Line and Substrate are blocked by conductor (3), and since the Gauss law gives:
the capacitance C12cond is reduced. Equations (1) and (2) give:


So equation 3 shows two counter-effects: an increase by dummies effect and a reduction by screening effect. They are shown in figure 11 depending on lD and nD for s0=2µm.

Figure 11. Capacitances (F) as a function of nD and lD for s0=2µm (ΔC12 in blue, Ccond12 in red, Cdum12 in green)

One notes Ccond12 decreases with lD due to the screening effect (eq.2). This screening effect is also more pronounced for a large nD shown in Figure 8 and Figure 11. Also the increase C12 due to the dummies effect has exactly a contrary variation. However this increase doesn’t compensate the decrease, resulting in a small decrease of Cdum12 (better shown in figure 6 than in figure 11). As a conclusion we would say that the screening effect is the dominant effect and is responsible of the decrease of the capacitance as a function of lD and nD.

If the term C12 of equation 1 is developed, an interesting conclusion can be made. Indeed the increase of capacitance is mainly due to the capacitance between Line and the closest dummies. This result is verified by defining 3 different layouts (see figures 12 to 14):

  • A layout with 4 dummies around the Line (Figure 12).
  • A layout like the previous one with 4 additional dummies (Figure 13).
  • A layout like the previous one where the 4 additional dummies have a rectangular shape (Figure 14).


Figure 12: first layout with 4 dummies around the Line.

Figure 13: second layout with 4 additional square dummies.

Figure 14: third layout with 4 additional rectangular dummies.




The values of capacitance Line/Substrate calculated by CLEVER are respectively:

3.434 pF, 3.424 pF and 3.417 pF.

So it confirms the additional dummies have a negligible effect on the final capacitance. As a consequence the design of dummies not close to signal lines is quite free and so can follow the CMP requirements.


VII- 3D Field Solver Comparison

We have compared CLEVER and STELLAR results on 3 different layouts. The results are comparable and shown in table 2. Layout 1 corresponds to Figure 3, layout 2 and 3 to Figure 4.


Layout 1
Layout 2
Layout 3

Table 2. CLEVER results versus STELLAR.


It is also important to notice that the simulation time is different between CLEVER and STELLAR due to the different numerical methods and the way to treat dummies. The average simulation time is a few seconds with STELLAR whereas it is a few minutes with CLEVER on a PC Linux 2.4 GHz AMD 64 bits processor. The observed average simulation time ratio, on the 64 layouts simulated, between CLEVER and STELLAR varies from 10 to 100.


VII- Conclusion

We have shown how capacitances calculation can be done taking into account dummy metal using two different field solvers: CLEVER and STELLAR. By using EXACT framework, the geometrical analysis of the dummies geometry on the capacitance value, has been easily done thanks to the extreme flexibility of EXACT (parameterized process and layout by using LISA script language). We have concluded that the “square-like” geometry minimizes the increase of the capacitance and that additional dummies (on the left and right hand side of the line) have a negligible effect on the capacitance increase. We would to conclude on the simulation time difference between CLEVER and STELLAR. CLEVER and STELLAR gave in this study the same results but with a ratio in simulation time from 10 to 100 in favor of STELLAR. We wanted to remember that CLEVER is designed for capacitance extraction on medium cell size with a very precise description of the 3D back end process, whereas STELLAR is designed for blocks with a less precise description of the 3D back end process. The different numerical methods used by CLEVER and STELLAR are thus responsible of this simulation time difference.


  1. EXACT: Interconnect Parasitic Capacitance Simulator from Silvaco, Simulation Standard Volume 13, Number 2, February 2003.
  2. Validation of CLEVER Interconnect Parasitics with 0.18um Process Measurements, Simulation Standard Volume 9, Number 11, November 1998.
  3. STELLAR – Process Based Parasitics Capacitance Extraction on Large Custom Cells: Overview and Features, Simulation Standard Volume 14, Number 4, March 2004.
  4. Calcul des Capacités Parasites dans les Interconnexions des Circuits Intégrés par une Méthode des Domaines Fictifs, Ph.D. Thesis, Sylvie Puteaux, 2001.
  5. An Efficient Algorithm for 3D Interconnect Capacitance Extraction Considering Floating Conductors, O. Cueto, F. Charlet, A. Farcy, pp.107-110, Proceedings SISPAD 2002.



Post-processing in CLEVER for dummy floating metal


To treat the dummies (floating metal) in CLEVER, the user could specify these dummies as made of a dielectric having a high permittivity. This solution is correct and works well in 2D for a limited number of dummies. But in 3D with a high number of dummies, the memory requirement becomes high and it makes this method inadequate.

So to overcome this limitation, another method considering dummies as regular conductor is presented here.

Physical and mathematical description
In a physical point of view, the problem solved by CLEVER can be wrote q = C.V

where q is the matrix of charges n x 1
  C is the matrix of capacitances n x n
  V is the matrix of voltages n x 1
  n is the number of conductors labeled from 1 to n.

In the case of a conductor:

Vi is known and qi is unknown.

And for a dummy:

Vi is unknown and qi = 0.

Let’s develop the matrix C:

C is symmetrical and non-diagonal coefficients are negative.

CLEVER gives all coupling capacitances

The sum of coefficients for each line is zero:

(matrix C is singular).

So, once CLEVER has computed the matrix C, the problem to solve consists in changing the matrices q and V to account for dummies. After a mathematical development, this procedure looks like a reduction of the matrix C by suppressing lines and rows corresponding to dummies. In the following, for simplicity reason, we are going to consider a simple case.


Simplified Case

We propose here to develop the post-processing procedure for a simplified case where k real conductors (k<n) are considered in a system where the matrix C is the same as above. These k conductors are assumed to be labeled from i=1..k. The matricial system is decomposed in blocks:

where the upper script T stands for the transposed matrix.

We split it in two systems:

Then the problem is reduced into:

and the non-diagonal coefficients of matrix

are the capacitances between the k real conductors when all others are dummies. They are the values searched. We can note that only one matrix inversion is needed. Moreover C3 is singular, so it can be easily inverted by a Cholesky decomposition making the inversion limited to the inversion of a triangular matrix. It means the extra cost required by this post-processing is negligible.


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