TCAD Simulation of a SONOS Device with Silvaco’s new FNONOS Model


Erasable programmable read-only memory (EPROM) devices include amongst others, floating gate technology and SONOS (Polysilicon-Oxide-Nitride-Silicon) technology. Floating gate technology involves charge being stored in the polysilicon floating gate as a continuous spatial distribution of free carriers in the conduction band. In contrast, SONOS gate stack structures involve charge being stored in spatially isolated deep level traps within the nitride layer. Floating gate technology faces a number of challenges with respect to scaling cell-size and program/erase voltages. The relatively thick tunnel oxide layer present in floating gate devices, whilst providing good data retention, yields problems with operating voltage requirements in that the voltages can exceed voltage limits of scaled CMOS devices. The desire for low power and low voltage memory devices has lead to the proliferation of SONOS devices for high density EPROMs. SONOS is desirable for its low programming voltages, endurance to erase/program cycling and compatibility with CMOS technology. SONOS devices are also able to show a 2-bit/cell storage scheme that utilizes different physical locations to store programmed charge.

Figure 1 shows a typical SONOS gate stack present in a SONOS MOSFET memory cell. The semiconductor (S) channel that forms has a thin layer of oxide (O), typically 2nm, grown onto it. This layer is called the tunnel oxide layer. Following this is a thin layer of silicon nitride (N), typically 4 to 5 nm thick. Following this is a thicker layer of oxide (O), typically 5 to 6nm thick. This layer is called the barrier or capping layer. Finally we have a semiconducting polysilicon (S) gate layer. The nitride layer is made up of trap rich nitride so that is has trapping levels located within it. The nitride-oxide band offset allows charge to be accumulated in the nitride layer.


Figure 1. Schematic diagram for gate stack.



FNONOS model

Silvaco’s ATLAS device simulator has a new model specifically created to allow the charge-erase behavior of SONOS structures to be simulated. For each point in the channel oxide interface the nearest distance to the nitride layer is calculated. The tunneling current for this point is then calculated as:



Jn is the tunneling current, E is the electric field, DV is the potential drop across the tunnel oxide layer (which is calculated automatically by ATLAS ) and BH.FNONOS is the barrier height. If BH.FNONOS is not specified ATLAS will also automatically calculate it. The above formulas make use of the WKB theory for the tunneling co-efficient through a trapezoidal barrier.

In the above, if DV>BH.FNONOS, factor1 and factor2 are both set to be unity. In this case equation (1) reduces to the expression for Fowler-Nordheim tunneling.

The FNONOS model also includes a capture efficiency factor, ETA.FNONOS, where the calculated tunneling current given by equation (1) is multiplied by ETA.FNONOS before it is added to the nearest floating electrode. The model also allows the efficiency itself to depend on the charge state of the floating electrode. This is enabled by setting the NT.FNONOS parameter on the model statement to a positive value. The efficiency is modified by:

where Qfloating is the floating gate charge density.


Device Simulation

The device is created using Silvaco’s device simulator ATLAS. It is also possible however to use Silvaco’s process simulator ATHENA to create the device using a physical process. The device SONOS gate arrangement structure is seen in Figure 2 (left) together with the net doping profile and the entire device structure Figure 2 (right). Currently the FNONOS model requires you to either set the nitride layer as a floating contact or to embed floating contacts in the nitride layer. It is possible to set up a number of floating contacts within the nitride layer, in this way some spatial information about the tunneling current can be obtained. The device in this simulation incorporates several floating contacts in the nitride layer.

Figure 2. Left: device gate stack, Right: Entire device with doping profile.


Figure 3 shows the IdVg curve for the device under initial conditions, i.e. not programmed or erased. To program the device 12V was applied to the gate and the drain contact was ramped to 8V over 1ns and then held there for 1us. The internal charge for each of the floating nodes in the nitride layer is shown in Figure 4. The IdVg data for the programmed device was then obtained. Finally, to erase the device the gate was set to -10V and the drain was ramped to 8V over 1ns and then held for 1us. Figure 5 shows the IdVg curves for the three different states. The middle curve is for the unprogrammed-unerased state, the right curve is for the programmed state and the left curve is for the erased state. For the program conditions applied, a shift in the Vt of the device is obtained. It is evident in Figure 5 that it is also possible to simulate an overerase where the curve for the erased device is to the left of the middle curve.

Figure 3. Drain current vs. gate voltage.


Figure 4. Internal charge for the four floating gates.


Figure 5. IdVg curves for the unprogrammed, programmed and erased states.



Silvaco’s device simulation framework has been used to simulate the program-erase of a SONOS device structure. The device structure was modeled using ATLAS syntax. In this simulation several floating electrodes were placed throughout the nitride layer in order to obtain information regarding the spatial distribution of trap charge. The phenomena of overerase can also be simulated. The FNOSOS model can be used to accurately tune program/erase conditions for SONOS device structures and hence optimize device structures.


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