Interconnect Parasitic Extraction of BiCMOS Cell Using Silvaco CLEVER


1. Introduction

Interconnect parasitic effects play a very important role in modern integrated circuit design, especially for digital circuit. This article presents how a cell level BiCMOS nand gate is extracted with R (resistances) and C (capacitances). The extracted RC result is then back-annotated into SPICE netlist for POST verification purpose. We used the Silvaco product, CLEVER which is a highly accurate 3D process interconnect RC extractor.


2. Description of BiCMOS Cell Extractor and Simulation Results

2.1 Overview

In order to perform parasitic extraction, we need a layout file and a command file. Command file defines the physical processes and starts the interconnect simulation. It also generate the 3D structure files and SPICE netlist. The layout file can be in the form of a GDS format. Besides, we may also need a layer mapping file which provides a name for each layer and a rule file which is similar to the technology file to define active device and connectivity. Figure 1 shows the data flow inside CLEVER. Figure 3 is the saved layout after loading the layer mapping file. The new layer names are showed in this layout.


Figure 1. CLEVER working structures.


nwell drawing 42 0 #NWELL
active drawing 43 0 #Active area
poly drawing 46 0 #Poly gate
pbase drawing 58 0 #Pbase
nselect drawing 45 0 #nselect
pselect drawing 44 0 #pselect
cont drawing 25 0 #Contact
metal1 drawing 49 0 #Metal1
buried drawing 38 0 #buried_n+

Figure 2. Renaming GDS number.

Figure 3. After loading renamed GDS file.


2.2 Layer mapping file and rule file (tech file)
To start, CLEVER loads the GDS format layout. We re-named its corresponding layer number by some meaningful names (Figure 2) for convenience. These layer names are used in defining the rule file. The rule file defines the connectivity between layers. It also defines both the active devices (we only used MOS and BJT in this article) and the passive devices (resistor diode and capacitor). Defining the rule file is the key to accurately extract the device geometry from a layout file. Here we will demonstrate a simple BiCMOS nand gate rule file which contains five NMOS transistors, two PMOS transistors and two BJTs.

And !nwell active NACTIVE
And nwell active PACTIVE
Not nwell PSD PSUB
Not !nwell NSD NSUB

The Boolean operations above define NMOS and PMOS transistors with substrate region (four terminal device). As for BJT, there are three types of BJT format in CLEVER.

  1. Collector type: Collector contains base, base contains emitter.
  2. Emitter type: Emitter contains base, base contains collector.
  3. Base type: Base contains collector and emitter.

We used the first type of BJT definition (collector contains base and base contains emitter).

And pselect pbase base1
And base1 active BASE
And nselect pbase emittor1
And emittor1 active EMITTOR
And nselect buried COLLECTOR1


2.3 Simulation Results
Once the layout file and rule file (technology file) are loaded, CLEVER will start the process simulation such as deposition, etching and lithography. There are two types of etching/deposition modes in CLEVER. Geometric mode allows the user to quickly build up the so-called “Manhattan” structures in which all regions have either vertical or horizontal faces. The physical mode is more accurate and is based on parameters such as etch/deposit rate, time, and others. It provides a generic way of simulating the physics behind process steps such as chemical vapor deposition (VCD), chemical mechanical polishing (CMP), or reactive ion etching (RIE). A 3D structure is created from the process simulation. The physical mode will take more time and memory while creating a more realistic structure. There is a trade-off between accuracy and simulation time. In our example, we use the more realistic physical mode.

The commands in Figure 4 demonstrate CLEVER loading a layout file which is the cell “nand_gate_new_exploded” in the GDS file “bicmos.gds”. It also loads a layer mapping file “” and a technology file “nand_gate.lmp”. The save command saves the renamed layout file and the initial netlist extracted from CLEVER by using the rule file. A more realistic lithography and deposition process is used for the active layer. Then the commands in Figure 5 save the 3D structure and performs interconnect analysis on the 3D structure. Figures 6, 7, 8 are the saved 3D structures. Finally, a RC netlist (Figure 9) is saved and will be included in a SPICE simulator such as SmartSpice (Silvaco Spice simulator).

Init GDS2=”bicmos.gds” Cell=”nand_gate_new_exploded” Layermap=”” Depth=1.0 Silicon Map=”nand_gate.lmp”

Save Layout=”nand_before.lay” Spice=””

## Process Description ##

Illumination Wavelenght=DUVLINE

Deposit Resist Thinknewss=0.1 max

Mask “active” Litho CriticalIntensity=0.1 Aperture=0.1 Defocus

Etch Silicon

Strip Resist

Deposit Oxide Thickness=0.0 max

Deposit Material(“gateox”) Thickness=0.01 max
Figure 4. Initial command file.


Figure 5. Command file used to perform interconnect analysis.


Figure 6. 3D structure after final process.


Figure 7. Top view with gate oxide layer.


Figure 8. Back side view with poly layer.


Figure 9. Part of post RC extraction netlist.


The parasitic effects are clearly seen from Figures 11 and 12. This waveform shows that functionality (Figure 10) is correct for a BiCMOS nand gate and time delays. This RC delay is critical for digital applications.


Figure 10. Waveform of initial netlsit without RC extraction


Figure 11. Comparison simulations between netlist with RC and netlist without RC


Figure 12. Zoomed in waveform comparisons



We have performed RC extraction based on a cell level BiCMOS nand gate using the Silvaco tool, CLEVER . CLEVER helps IC designers extract accurate RC parasitics for both active and passive devices on the layout level. With physical processes integrated with layout, users can use CLEVER to investigate and improve the cell level layout design and minimize parasitic effects. The 3D structure extraction ability can also help the designers to visually modify their structures after verification.


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