HIPEX-CRC Parasitic RC-Network Reducer



Design of large scale chips requires precise knowledge of interconnect delays. However, detailed analysis of interconnects may quickly become computationally too expensive due to the distributed nature of the networks, and the large number of internal nodes extracted.

HIPEX-CRC is a parasitic RC-network reduction tool able to reduce the huge number of elements produced by major EDA parasitic extractors, including coupling capacitors, and supports main industry standards parasitic formats.

Advanced algorithm behind HIPEX-CRC enables to maintain accuracy within a few percents of Spice. HIPEX-CRC can be directly plugged to the HIPEX suite, but also can be used as a stand-alone tool.


Scattering-Parameter-Based Macromodeling

  • HIPEX-CRC allows the user to preprocess the circuit, making a first equivalent reduction by merging serie-parallel elements and removing dangling elements
  • Once the preprocessing is done, HIPEX-CRC relies on a powerful Scattering-Parameter-Based Macromodeling [1] reduction technique. The advanced node merging rules within HIPEX-CRC lead to the partitioning of the original network into a set of several N-port component, each of which is then modeled by a reduced RC circuit characterized by the same set of S-Parameters (Figure 1)
Figure 1.
  • This permits the analysis of interconnect models other than RC-trees, and therefore, coupling capacitors and resistor loops can be handled without loss of generality
  • Also, partitionning of the circuit into small multiport components leads to smaller size matrix computation, saving time and memory, while increasing accuracy
  • Output of HIPEX-CRC is thus a realizable, simulable reduced network. Figure 2 depicts the HIPEX-CRC reduction flow
Figure 2. HIPEX-CRC flow.


Key Features

  • HIPEX-CRC supports SPICE, DSPF and SPEF input formats and outputs SPICE, DSPF and SPEF reduced netlists. Possibility is given to the user to output SPEF from DSPF input, as well as output DSPF starting from a SPEF output
  • HIPEX-CRC is fast: SPICE netlist ranging about 1.5 million parasitic elements can be processed within some 5 minutes on a 64bit-Linux standard machine
  • For enhanced reduction, HIPEX-CRC may ignore all parasitic resistances and/or capacitances lower than a user-specified threshold. Also, HIPEX-CRC may ignore coupling capacitors present in DSPF or SPEF netlists
  • For selective reduction, HIPEX-CRC may ignore user specified subcircuits and/or SPF nets.
  • For custom reduction, HIPEX-CRC enables the user to specify unreducible nodes, to control topology of the circuit
  • Any reduction step performed by HIPEX-CRC is reported to a summary file (detailed or simple, on the user choice)
  • HIPEX-CRC is easy to use, thanks to user-friendly graphical interface, and flexible LISA scripting language
  • HIPEX-CRC is available for Unix, Linux32-64bit, Windows


Examples and Validation

1. Example #1
The RC tree network shown in Figure 3 is made of 26,000 elements (13,000 R and 13,000 C). A set of 10 external ports was specified to carry out the reduction.

Figure 3.

Symbol in dashed inset stands for a lumped RC segment of 1000 resistances of 0.16 Ohm, and 1000 capacitances of 5e-4 pF.

A reduction of 99.7 % was achieved on this circuit, with 42 resistances and 32 capacitances in the reduced network.

Figure 4 is the snapshot of a comparative SmartSpice transient simulation of the original RC tree network versus its reduced equivalent.

Figure 4.

Worstcase voltage precision of the reduced circuit lies within 2.5 % from that of original, while simulation time was divided by 400.


2. Example #2

The RC tree network shown on Figure 5 is made of 80,000 elements (40,000 R and 40,000 C).

Figure 5.


A set of 6 external ports was specified to carry out the reduction.

Symbol in dashed inset stands this time for a lumped RC segment of 4000 resistances of 0.25 Ohm, and 4000 capacitances of 15e-6 pF.

Again, a reduction of more than 99 % was achieved on this circuit, with only 16 resistances and 15 capacitances in the reduced network.

The comparative SmartSpice transient simulation of the original RC-tree network versus its reduced equivalent is shown on Figure 6.

Figure 6.


Though only 6 external ports were specified, the worstcase voltage precision was no less than 2.5 % again, and simulation time was divided by 3000.


3. Example #3

Figure 7 is the snapshot of SmartSpice transient simulations of reduced and original DSPF formatted industrial networks.

Figure 7.


The original network is made of 560 nets, for a total number of 34,464 RC elements.

HIPEX-CRC performed the reduction net by net ; percentage of reduction per net varies from 48% to 82%, according to the topology of the net (regularity, fan-out of internal nodes, ...etc), and the number of instance pins or pins connected to it (the external ports).

Percentage of reduction for the global circuit was found to be 71.6 %, and simulation time could be reduced by 50%.



HIPEX-CRC is an accurate,fast and flexible tool. Based on Scattering Parameter Macromodels, the technique behind guarantees the resultant equivalent network to be fully compatible with general-purpose simulators. Simulation time can be reduced by two or three orders of magnitude, while the response of the reduced circuit is within a few percents of that of the original network.


  1. `Partitioning and Reduction of RC Interconnect Networks Based on Scattering Parameter Macromodels’, H.Liao and W. Wei-Ming Dai, Computer Engineering, University of California, Santa Cruz.

Download pdf version of this article