A Sophisticated Verilog-A Debugger


During the elaboration of a Verilog-A model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO Verilog-A debugger has been designed to meet these needs. It is available since version 2.6.0.R of SmartSpice and works along with SILVACO C-Interpreter. It allows iteration-per-iteration Verilog-A modules debugging. The debugger is tracing all the Verilog-A instantiations of the design, either instances of the SmartSpice netlist or in other Verilog-A modules.

The BSIM4 Verilog-A model (bsim4.va) and the adder design (adder.in) used as an example are freely available on SILVACO website.

It can be enabled by setting in the input deck:

.OPTIONS va_mode=debug

The debugger appears when the simulation of this input deck is launched. The simulation stops at the first instruction (a breakpoint at the first instruction is always set by default). In the case of BSIM4 model, the first instruction encountered is the initial_step event in the analog block. The layout of the main window at startup is shown in Figure 1.

Figure 1. Debugger window layout.

The Verilog-A source code is displayed in an editor window. Syntax highlighting is available and its colors are fully customizable. Line numbers can be displayed by checking the “Show line number” box in the Properties dialog window (Edit > Properties...).

The console window is at the bottom of the main window. The error messages are printed in this area and the user can enter commands manually.

In this example (Figure 2. The console window), a breakpoint has been set at line 2699 (the end of the initial_step block) and the simulation has been started with the cont command. The edit window has now the aspect shown in Figure 3.


Figure 2. The console window.


Figure 3. Editing window.


I. Tracing Code in the Source Code Window

Verilog-A code in a module can be debugged step-by-step or by using breakpoints. Breakpoints can be set by opening the “View breakpoints...” window or by a direct insertion in the Verilog-A code using “insert/remove breakpoint” button . In the first method, a breakpoint condition can be set in the condition field. This condition can be of several kinds: it can include logical, relational, bitwise, shift and arithmetical operators as well as mathematical and simulation-related functions, shown in Table 1.

Function Name Description
Analysis type. arguments must be “DC”, “AC”, “NOISE” or “TRAN”
Initial iteration. arguments must be “DC”, “AC”, “NOISE” or “TRAN”
Final iteration. arguments must be “DC”, “AC”, “NOISE” or “TRAN”
Current simulation time in transient analysis
Current circuit temperature

Table 1.

$realtime function can be of a great help for debugging a model on a given time range. Supposing now that the Bulk-Drain diode current value of a BSIM4 device has to be checked for a time > 190 ns. A breakpoint is set in “View breakpoints…” window at line 2878 (the end of the bulk diodes calculations). The condition for this breakpoint entered in next figure stops the simulation during a transient analysis if time > 190 ns. The other breakpoints are removed using ‘Delete’ button in the same window (Figure 4).

Figure 4. Add a condition to a breakpoint.


By using “continue” button , the simulation continues and the debugger stops when time has reached 190 ns. The current analysis and the current step (time in the case of a transient analysis) are printed at the bottom panel of the main window:

Figure 5. The bottom panel.


DC, AC, TRANS or NOISE can be displayed at this location according to the analysis run. The simulation step can be the sweep value for DC analysis, the time for transient or the frequency for AC and NOISE. Cursor location information in the source code window is also given.

“step into” and “step over” buttons on the upper toolbar can be used to trace into or over the user-defined functions. Setting a breakpoint on a given function can be done directly in the “View breakpoint...” window by inserting the function name with “In function” box checked.


II. The Variable Watch Display

Once the debugger has reached the desired breakpoint, the value of ‘cbd’ (Bulk-Drain diode current) can be checked. Moving mouse cursor over the variable in the source code window prints its value at current SmartSpice engine iteration and current location in the module:

Figure 6. Variable value display in edit window.

Another way to display the ‘cbd’ variable is to look for this variable in the local variable panel:

Figure 7. The local variables panel.


The local variable panel shows all the variables, parameters and branch quantities values in the current context (initial block, analog block or user-defined function). These values are updated at each step. The panel next to it shows the global variables related to current simulation. The running analysis as well as its parameters, the SmartSpice engine iteration counter and the circuit temperature are given.

Figure 8. The global variables panel.


A third way to display ‘cbd’ value is to use the ‘watch’ panel next to the global variables panel. In this window, only the variables asked by the user are displayed. To do so, the name of the variable must be entered in the watch dialog box (Figure 9. The Add Watch dialog window). Entering for example ‘cbd’ variable in the Add Watch window has the effect of adding the variable to the current list of variables in the watch panel (see Figure 10. The watch panel).

Figure 9. The Add Watch dialog window.


Figure 10. The watch panel.


By using this latter method, the value of cbd can be easily monitored during the simulation. The values of the asked variables in the watch panel are re-evaluated at each debugger step.


III. The Call Stack Display

The call stack window displays the debugging location inside the instance hierarchy. The following example is a PLL Verilog-A module instantiated in the SmartSpice netlist. This module is itself composed of other Verilog-A modules (generator, phase detector, low-pass filter and VCO). The hierarchy of the modules is:


Next figure shows the call stack content:


Figure 11. The call stack display.


Each level of the stack is of the following kind:

[level] instance_name(module_name), line_number file_name

The level [0] is the SmartSpice netlist launched with the simulator. The other stack levels can be a module instantiation within another Verilog-A module or a user-defined function. By double-clicking on a level of the stack, the associated module is opened in the editor window and the user can see where the next object in the stack is instantiated. The last level of the call stack indicates the current debugging location in the object at the bottom of the hierarchy. In the case of the PLL example, the objects related to the stack are:


Figure 12. An example of the hierarchy structure of the call stack



Using a debugger can be of a great help when prototyping a model or when debugging a circuit design which includes Verilog-A modules. Its great readability and ease of use allow the user to quickly find physical inconsistency in the model equations or in the circuit design. The call stack window helps the user to navigate easily through the design hierarchy.


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