SET Accurate Compact Model for SETMOSFET Hybrid Circuit Simulation
C. Le Royer*, G. Le Carval*, M. Sanquer**
* CEADRTLETI  CEA/GRE, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
cyrille.leroyer@cea.fr, gilles.lecarval@cea.fr
** CEADRFMC, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
marc.sanquer@cea.fr
The following article, by Le Royer, C., Le Carval, G., Sanquer, M.: SET Accurate Compact Model for SETMOSFET Hybrid Circuit Simulation. In: Wachutka, G., Schrag, G. (eds.), Simulation of Semiconductor Processes and Devices 2004. Wien  New York: Springer. 2004 (http://www.springer.at/main/book.jsp?bookID=3211224688), demonstrates the flexibility of SmartSpice used with its module VerilogA in the simulations of SET circuits and hybrid SETMOSFET circuits.
Abstract
SingleElectron Transistors (SETs) [1][2] are attractive candidates for postCMOS VLSI ICs. Accurate models are also required in order to efficiently design SET circuits and hybrid circuits. We have developed a new physical compact model of SET [3][4], which enables the accurate simulation of SET circuits and hybrid circuits in a SPICElike environment. We show advanced examples of applications of our approach: simulations of elementary circuits which functionalities have been experimentally demonstrated in the literature [5][6].
1 Introduction
SETs have attracted much attention because of their low power consumption and small size [1][2][7]. Recent works [5][6] show that SingleElectron Transistors could enable innovative functionalities if they are associated with MOSFETs. However MonteCarlo (MC) simulation [8] is not adapted to the analysis and the optimization of realistic logic circuits with a large number of devices (MOSFETs and SETs).
In this paper, we propose a compact physically based SET model, describing SET characteristics accurately over a wide range of temperature and voltages [4]. Our approach is simpler and more efficient than those presented in the literature [9][10]. Our model has been validated in static and dynamic regimes [4], at both device and logic circuit levels, by comparison with the MC simulator SIMON [8].
2 SET Modeling
Our model is derived on the basis of the “orthodox” theory of single charge tunnelling and the master equation method [1][2]. The number of elementary charges e in the SET island (Figure 1.a) is supposed to be n = 1, 0 or +1. This model (detailed elsewhere [4]) is built on this assumption and the periodicity of the current I_{DS}(V_{GS}) : the average I_{DS} current (Figure 2.b) is determined as a function of the V_{DS} and V_{GS} voltage, the temperature and the offset charges, q_{0}.

Figure 1: a) Schematic representation of a SingleElectron Transistor. b) Example of current I_{DS} calculated with our model. The blockade regions (diamond shape) can be clearly distinguished. 
We have checked that, in the dynamic or static regime, the difference between ourmodel and MC simulation (Figure 2) is less that 1.5% for V_{DS} ≤ 2e/CS (C = C_{1} +C_{2} + C_{G} is the total capacitance of the central island), which is two times the limit of the models proposed by Uchida [9] or Mahapatra [10]). We have checked that thisresult does not depend on the SET parameters (capacitances, resistances) and isvalidated for a large range of temperature (kT / E_{C} < 0.1).

Figure 2: a) Example of relative error (%) between MC simulation and
our model in the V_{DS}V_{GS} diagram. In the central
region the accuracy is better than 1.5%. b) Theoretical limits of validity
of our model (which correspond to the MC results). 
3. Applications to Hybrid MOSFETSET Simulation
3.1 Ring Oscillator with SETs
The first logic gates that we have simulated with our
model (in SmarSpice with VerilogA
[11]) are ring oscillators composed of 2p+1 SET inverters [11] (Figure 3).

Figure 3: Ring oscillator with 3 SET inverters. 
The voltages V_{1}, V_{2} and V_{3} are the outputs of the 3 inverters. The supply voltages are +V_{D} and V_{d}. This circuit generates oscillating signals like in the case of CMOS inverters. Figure 4 shows the voltages of the outputs of the three inverters as a function of time, obtained by a SmartSpice simulation [11]. This proves that our model allows to simulate this oscillating behaviour.

Figure 4: Simulation of the ring oscillator behaviour. When the supply
voltage Vd is increased 
3.2 Hybrid SETMOSFET Circuits
We have also simulated the electrical behaviour of two
hybrid MOSFETSET circuits: a SRAM cell [5] and a “quantizer” [6]
(Figure 5) proposed by Inokawa.

Figure 5: Schematic circuits proposed by Inokawa a) SRAM cell [5] (the multiplevalue memory effect is due to the VI hysteresis). b) “quantizer” [6] (the signal Vin is sampled with respect to the frequency defined by the “Clock” MOSFET along the stability points a, b, …, f). 
For most simulation parameters, we have considered the values
extracted by Inokawa from measurements. We have used the following values: MOSFET:
L = 14µm / W = 12µm / T_{ox} = 9.45nm  SET : C_{J}
= 1.8aF / CG = 0.07aF / Rt = 150k /
q_{0} = e/2 / V_{gg} = 1.04V[5].
The simulated results (Figure 6 and Figure 7) show a very good agreement with
these experimental measurements [5][6].

Figure 6: a) Current characteristic I(V) of the subcircuit of the SRAM cell calculated by hybrid SPICE simulation. b) Multivalued hysteresis effect of the SRAM cell simulated by our model. 

Figure 7: Simulation of the quantizer operation.
The output voltage V_{out} (with a staircase shape with respect
to the stability points) corresponds to the sampling of the triangular
voltage V_{in}. 
4 Conclusions
In this paper we propose a new compact model for SET dedicated to SPICE simulation for SET circuits and hybrid MOSFETSET circuits. After showing the performances of our model, we apply it to the simulation of SET Logic gates and hybrid MOSFETSET circuits. We demonstrate the accuracy of our model by the good comparisons between the SPICE simulations and the experimental measurements of these circuits [5][6].
Acknowledgment
The authors would like to acknowledge Silvaco’s contribution which greatly facilitated implementation of these models within SmartSpice and VerilogA.
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