Parasitic Capacitance Extraction with HIPEX and EXACT
Overview
To extract parasitic capacitances from a circuit layout, you need to perform the following steps:
 Define the technology process and material data. This includes
vertical order of mask layers and dielectrics, their thicknesses, conductivity,
and permittivity constants.
 Use the technology data as input to a 2D or 3D field solver
to obtain capacitance coefficients.
 Generate a rule file for a fullchip capacitance extractor
using the obtained capacitance coefficients.
 Run the capacitance extractor using the generated rule file.
Silvaco provides tools for performing all the steps above. You can use EXACT for steps from 1 to 3 and HIPEXC for step 4.
EXACT is a 3D field solver powered by a 3D process simulator to accurately represent the crosssections in the physical chip, rather than using square crosssections. This maximizes the accuracy of the capacitance coefficients because the calculated capacitance is derived from realistic crosssections and 3D shapes. See [1] for more information.
HIPEXC is a fullchip parasitic capacitance extractor. It is a part of the HIPEX fullchip extractor, which also includes the layout netlist extractor, HIPEXNET, and the parasitic RC extractor, HIPEXRC. HIPEXC works with a stripe database produced by HIPEXNET. This database divides the original layout into stripes making parallel processing possible. The stripes also make it easier to process huge layouts on a single host machine, one stripe at a time. HIPEXC is a fast 2D extractor. It uses thirdparty coefficients to derive capacitance from the extracted parameters of parasitic area, length, and distance. See [2–3] for more information.
Builtin Model
HIPEXC, as well as the most fullchip capacitance extractors, considers the following parasitic capacitance effects:
 Area capacitance is a surfacetosurface capacitance between two overlapping polygons on different layers (see A in Figure 1).
 Fringe capacitance is an edgetosurface capacitance between two overlapping polygons on different layers (see Fu and Fd in Figure 1). The limit case of a fringe capacitance is a capacitance between exactly coincident edges (see Fc in Figure 1).
 Lateral capacitance is an edgetoedge capacitance between two adjacent polygons on the same or different layers (see L1 and L2 in Figure 1).
Figure 1. Parasitic Capacitance Effects. 
In EXACT, you use a combination of test structures to extract the coefficients for all the parasitic capacitance effects. Each of the test structures is specifically designed to highlight one of the three effects. The coefficients can then be mapped directly to HIPEXC (or any other fullchip parasitic tool) extraction statements. EXACT provides powerful scripting capabilities to convert numeric results generated by the 3D field solver to a rule file for a fullchip extractor. EXACT comes with a set of readytouse scripts that generate rule files for the most popular fullchip extractors, including HIPEXC from Silvaco.
Table 1 shows the coefficients, which EXACT calculates for HIPEXC extraction statements (layer1 is above layer2).
Coefficient 
HIPEXC Capacitance Equation 
HIPEXC Statement 
K_area,pF/um2 
K_area * <overlapping layer1 and layer2 area> 
CUP OVERLAP 
K_fringe_down,pF/um 
K_fringe_down * <layer1 perimeter overlapping by layer2> 
CUP OVERLAP 
K_fringe_up,pF/um 
K_fringe_up * <layer2 perimeter overlapping by layer1> 
CUP OVERLAP 
K_coincident,pF/um 
K_coincident * <coincident perimeter of overlapping layer1
and layer2> 
CUP OVERLAP 
K_lateral,pF/um 
K_lateral * <common length of edges within lateral effect
on the same layer> 
CUP LATERAL 
Table 1. Capacitance Coefficients.
All the coefficients, except K_area, are functions of lateral distance D. The area coefficient is a constant. For the lateral coefficient, the following equation is used:
K_lateral = n1 / (D + n2)^n3.
For all the fringe coefficients (K_fringe_down, K_fringe_up, and K_coincident), the equation is in the form:
K_fringe = n1 * (1 – exp(–n2*(D + n3))).
Here, n1, n2, and n3 are nonnegative constants calculated by the EXACT curvefitter. These constants are different for each capacitance effect and layer combination.
The fringe coefficient equation is designed specifically to account “chargesharing” effects. Consider Figure 1. The value of the fringe capacitor Fu is highly affected by the presence or absence of the Metal1 polygon at the left. If the left Metal1 edge is moved to the right, then some of the electrical field lines of the capacitor Fu will run from the right Metal1 edge to the left Metal1 edge, rather than to the Metal2 surface above. Therefore, the value of the capacitor Fu decreases. In HIPEXC, the extracted value of the lateral distance D decreases, and so does the value of the fringe coefficient K_fringe_up.
Figure 2 shows a HIPEXC rule file generated by EXACT. Vertical order of layers is METAL2, METAL1, POLY1, SUBSTRATE.
METAL2, METAL1, POLY1, SUBSTRATE.
cup Overlap
0.454623; cup Overlap
0.22762; cup Overlap
cup Overlap
cup Overlap
0.213182
cup Lateral
cup Lateral
cup Lateral

Figure 2: Example of HIPEXC rule file generated
by EXACT.
UserDefined Models
In HIPEXC, you can code your own equations for each of the three parasitic capacitance effects. To do so, you use LISA (Language for Interfacing Silvaco Applications) procedures in a HIPEXC rule file. When using your own capacitance equations, you have the additional option OUTSIDE_LAYERS for the CUP OVERLAP and CUP LATERAL statements. It specifies layers that are above and below primary layer(s). Neighboring layers affect the capacitance values due to the chargesharing effects between capacitances of different types. HIPEXC extracts lateral distances and widths of the specified outside layers such that you can use them in your equations.
In EXACT, you can calculate capacitance coefficients for arbitrary layer configurations. Then, you can write a LISA script that converts the numeric data obtained by the 3D field solver to the userdefined equations in the HIPEXC rule file.
References
 “Exact2: Interconnect Parasitic Capacitance Simulator
from Silvaco”, Simulation Standard, Volume 13, Number 2, February 2003.
 “Parasitic Resistor Extraction with HIPEXR”,
Simulation Standard, Volume 13, Number 9, September 2003.
 “HIPEXNET: New SILVACO FullChip LPE Tool vs. Maverick”,
Simulation Standard, Volume 13, Number 9, September 2003.