Silvaco’s RFIC Design Suite



This article focuses on the use of Silvaco’s RFIC Design Suite including PDK, SmartSpice-RF, and Gateway.

Silvaco Process Design Kits (PDKs) have been developed to help start the analog and mixed signal design cycles. The design kit supplies you with all the foundry process specific models, symbols, simulation setup for the Silvaco set of design tools.

SmartSpice-RF Harmonic Balance based Simulator provides a complete set of steady-state analyses and measurements to design GHz range RF wireless application ICs. It accurately and efficiently simulates noise, gain compression, harmonic distortion, oscillator phase noise, and intermodulation products in non-linear circuits using SPICE netlists.  

Gateway is the schematic entry for the Analog/Mixed Signal/RF Design design environment. The Gateway schematic is netlisted for SmartSpice-RF and tightly integrated for running simulations concurrent with the schematic.

This article shows the basic steps needed to take a design from schematic entry to simulation using the TSMC 018 MM/RF process and a set of Silvaco tools. These steps can be broken down into the following tasks.

  • Set up Gateway with the TSMC 018 MM/RF schematic files to load an example circuit. The example here is the Low Noise Amplifier (LNA) Circuit
  • Perform the circuit simulation from the Gateway Schematic Window. Before you perform a simulation, include the TSMC_cm018 model library from TSMC into the netlist. The LNA circuit is simulated and waveforms are displayed within SmartView


How to Run SmartSpice-RF in Gateway

To use the environment for schematic, simulation, and post-processing, the following licenses are required:

  • Gateway
  • SmartSpice -RF
  • SmartView

The following example is for an LNA simulation using SmartSpice-RF:

  1. To create a schematic in Gateway, first load one or more schematic symbol libraries. The example circuit that we’ve designed, the LNA Circuit, uses two different symbol libraries: spicelib and TSMC_cm018. The TSMC_cm018 kit symbol library contains process dependent symbols. spicelib (Silvaco’s library) contains basic schematic symbols for example, pins, and grounds. (Figure 1)

    Figure 1. Schematic and Symbol Libraries.

  2. Open the control deck window by selecting Simulation ->Input Deck ->Control Deck … in the Gateway pull-down menu banner to set up simulation environment. (Figure 2)

    Figure 2. Control Deck.

  3. Then, generate a SmartSpice-RF netlist from the Gateway menu banner by selecting Simulation-->Netlist-->SmartSpice. The SmartSpice-RF netlist will then appear (Figure 3).

    Figure 3. The netlist in SmartSpice-RF format.

  4. Simulate the schematic and view the waveform. (Figure 4) (Figure 5) (Figure 6)
Figure 4. Noise Figure and S-Parameter plots displayed in SmartView.


Figure 5. P1dB curve displayed in SmartView.


Figure 6. IP3 curves displayed in SmartView.



By using PDK, SmartSpice-RF and Gateway together, some of the specs for LNA like S-Parameter, Noise Figure, P1dB and IP3 can be easily simulated with high accuracy and reasonably run-time. In addition to those simulation capabilities, SmartSpice-RF can also characterize other RF circuits as well which really provides designers with the means to reduce time to market.


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