Role of Netlist Extraction in PDKs


Netlist extraction and the quality of netlist extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate of accurate netlist extraction. This simulation standard will detail this important area of netlist extraction and will provide an insight into Silvaco International’s netlist extraction tools to aid the circuit design engineer.


The Role of Netlist Extraction

What is NLE in a PDK?
A critical procedure in Custom/Analog Integrated Circuit Design Flow is Layout Netlist Extraction. Of particluar importance is the accuracy and completeness of the Layout Netlist Extraction for a productive design flow. Your design center may be staffed with the brightest circuit designers and use the most accurate models in the industry, however, your project will not be guaranteed first spin success with your silicon unless your PDK (Process Design Kit) contains a proper system for Netlist Extraction. First spin success is essential for meeting the demands of an ever diminishing required time to market, beating out your competition and producing a working product for your customer. The Extracted Netlist provides the means for physical verification. It’s superior properties deliver the fastest, most cost effective way of debugging your circuit thus minimizing expenditure. Simply, make sure it is correct before you commit it to silicon, it is a direct descendent of the old phrase, “Measure twice, cut once”.

What is an Extracted Layout Netlist?
One must have a general familiarity with the netlist before an Extracted Layout Netlist will have any meaning. A netlist is a file which describes electrical components and their interconnect. It is used primarily for simulation. A netlist can be created by a variety of methods. Most commonly, a netlist is created from a schematic entry tool. This is called a schematic netlist. A Layout Netlist is a netlist that describes an integrated circuit layout, while an Extracted Layout Netlist is a netlist that describes an integrated circuit layout, and is automatically created from the layout.

What is a layout netlist used for?
An extracted layout netlist is primarily used for physical verification (Figure 1). This physical verification can manifest itself in several ways. A common and efficient means is LVS (Layout vs. Schematic) verification. This is done to ensure that the semiconductor layout represents the circuit design. In many businesses, there are two separate staff: one that implements the mask layout and one that designs the circuit. LVS is the safety check that ensures that the mask designer has created a circuit layout that properly represents the circuit designer’s intent. This is very comparable to a building inspector making sure the carpenters have followed the architect’s plans. Another use for the Extracted Layout Netlist is Post Layout Simulation. The circuit designer can perform simulation testing on the physical mask layout. This can not only determine if the circuit, as it is laid out, works, but can also incorporate parasitic circuit elements that are now present in the physical circuit as a result of the layout style. These parasitic elements can affect the performance, and post layout simulation can be used as a final check to determine if the circuit design still falls within the targeted datasheet specifications.

Figure 1. Physical verification flow.


What creates a layout netlist?
A layout extraction engine processes the layout to create a layout netlist. The generic terminology for this tool is a NLE or a netlist extractor. Silvaco International offers two different NLEs. Our first product is Maverick, which is a flat netlist extractor. It processes the layout by first flattening it, and then determining the devices and interconnect. This works well for smaller integrated circuits with less than 50,000 components, but as circuits get smaller and more complex, a flat NLE starts to suffer noticeable speed penalties. To overcome this problem, Silvaco International has developed HIPEX-NET which utilizes a hierarchical approach to NLE. Through this novel hierarchical approach, the NLE can therefore take advantage of repetitive structures which is of paramount concern for large layouts that feature repetitive cells. For example HIPEX-NET successfully extracts layout hierarchical netlists with several millions devices on Win32 platform. The layout HIPEX-NET netlist is extracted in a fraction of the time and is fully compatible with Guardian LVS (Figure 2).


Figure 2. Example of Extracted Layout
Netlist obtained by HIPEX-NET


What Data is Processed?
A NLE requires a number of elements in order to extract the netlist. The first, obviously, is a layout. With a layout, there comes an assignment of process-dependent GDSII layers. The skilled layout designer can create masks to create devices using these GDSII layers. The next element of importance is the technology file. Within the technology file, there are three important pieces of information the NLE uses to extract the netlist from the layout. It contains layer generation rules for creating pin layers and ID layers, as well as the device definitions that are comprised of the layers. The wiring interconnect information also resides within the technology file. An example of a technology file for HIPEX-NET is shown on Figure 3.


Figure 3. Fragment of technology file for HIPEX-NET.


How is a Device Recognized?
The goal of the NLE is to locate and generate a netlist of devices that are located within the layout. A device is defined by an ID layer, a device type and its corresponding pin layers and is summarized in figure 4. For example, an n channel MOSFET can be defined by the ID layer NMOS_ID and its corresponding pin layers NMOS_S/D, Gate and P SUBSTRATE, where as a p channel MOSFET can be defined by the ID-Layer PMOS_ID with its corresponding PMOS_S/D, Gate and NWELL. These characteristics can be setup using the device setup form as shown in figure 5. This form is then used by the NLE running within the Expert environment. For example, the NLE scans the layout in order to identify ID layers as defined by the user. Each and every occurrence in the layout where it identified an ID layer, the NLE checks to see that all the necessary pins (those defined in the device definitions section of the technology file) are touching the ID layer. If this condition is met, we say that there is a recognized device, and the NLE will place this device in the netlist.


Figure 4. Example of ID and PIN layers for MOS transistors.


Figure 5. Example of Expert Device Setup form.


Factors Affecting Netlist Extraction Performance

How can we rate the quality of device definition?
Quite Simply, in two ways: Speed and Accuracy.
The accuracy can be a limiting factor in the versatility of the PDK. Some PDK developers lack the knowledge of device physics, and produce code that restricts the layout styles of the intended devices, they consider only the device and not the process itself. This means that some NLE code will only extract a device if the layout is drawn in a certain fashion. This can severely restrict the freedom of a designer to create custom layouts, and specially tailor the device for its applications. This can prohibit the use of the most robust and compact layout, which can be a penalty in both cost and performance. This phenomenon is very prevalent in Bipolar Devices and special applications of devices such as power, high current or precision matching. This lack of device physics knowledge in the NLE code not only limits its ability to recognize a variation of a certain device, but can also cause failure to recognize unintended devices such as parasitic bipolar transistors or tub diodes. The accuracy of NLE code PDK can therefore affect the size of your layout, and also fail to recognize unintended devices which may prevent the circuit from properly operating.

The speed, or the time it takes to extract a netlist, is dependent on the size of the layout and the number of devices in the process. The speed can be optimized in a number of ways. The first way is to use a minimal amount of layer operations to define the pin and ID layers. This means it is good to use the same layer for several pins of different devices, i.e. an n-well is the body of a p-MOS, a collector of an NPN, and the base of a PNP device. Another way to optimize the speed is to pay attention for duplicate layer operations in different pin or ID layer definitions, and make them global. The time savings through these optimizations may seem trivial, but as the device count goes up, and designs go through the iterative process of verification, debugging and updating on their way to tapeout, the time savings become evident.



This simulation standard has described netlist extraction using advanced netlist extraction tools. Through sophisticated algorithms layouts can be analyzed with great speed and accuracy through the use of advanced netlist extraction tools provided by Silvaco International.

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