Interconnect Parasitic Accuracy & Speed Improvements in New CLEVER Release


This article introduces the new features and numerical schema implemented in the most recent release of CLEVER from Silvaco. In this new release, both memory handling and simulation time are optimized to allow the input of larger simulation structures. In addition, the release offers greater control over the accuracy benchmarks necessary for extracted parasitic elements.

Parasitic Extraction Accuracy

Accurate parasitic extraction is crucial for deep submicron designs. Today, 3D field solvers are touted as the benchmark of accuracy, but any field solver is only as accurate as its input geometry. CLEVER achieves greater accuracy by using a combination of 3D process simulation and 3D field solver capabilities. All back end processes, including deposition, etching, and lithography, are performed before generation of the final structure geometry. This makes it possible to obtain an accurate 3D topology of the layout, while offering greater power and flexibility in extracting highly accurate parasitic resistances and capacitances in deep and ultra-deep submicron designs. (Figure 1)

Figure 1. The parasitic extraction overview in CLEVER.

Software applications that provide numerical solutions of real physical problems are often unable to correctly solve all problems put to them. Adaptive solutions that make use of user-provided tolerance specifications will solve most problems within the specification, but over-refined problems may waste valuable computation time. Problems that lack sufficient refinement may only appear within the user-defined tolerance specification, but actually are not.

Silvaco has solved this problem with the introduction of an accuracy switch in the new release of CLEVER that is used with respect to the tolerance level required for the parasitic extraction. The user defines the accuracy criterion. For simple problems, the user may choose to use relatively loose criteria. For difficult and complex problems, such as designs with high interconnection density, more rigid criteria will help to ensure an accurate output.

Let’s illustrate with an example. If a user requires a 1% margin of accuracy over a 3D structure, the numerical solver should present a solution that is within that 1%. If uniform criteria are used to estimate the error, the user will typically achieve 1% accuracy for most problems. This is because the mean error for the entire structure is less than the specified error value. This, however, is misleading. There is no guarantee that the user will achieve 1% accuracy for all problems over the totality of the 3D structure. While the software may report a total 1% accuracy margin, this result may not be locally applicable to the problem at hand. The additional accuracy switches solve such problems. The goal is to align the software’s predicted error with the actual error by adjusting the error criteria for what are very different physical problems.

The ‘Adapt’ parameter defines the accuracy criteria for both capacitors and resistors. The example below instructs the solver to compute both extractions with a single command:

Interconnect Adapt = (0.05 , 0.05)

The solver will then extract ALL parasitic interconnections within the user’s required 5% accuracy (the default extractable minimum values are 0.01 Ohm for resistors and 1E-18 F for capacitors).

This new version of CLEVER also offers user control over convergence criteria in addition to the adaptive control parameter. If the accuracy requirement is loose, the convergence is quicker. Tight requirements will slow the convergence down.

The five criteria for capacitance extraction are very loose, loose, fair, tight, and very tight. The three criteria for resistance extraction are loose, fair, and tight. The default levels for both capacitance and resistance are set to fair. The following is an example of these parameters:

CAPaccuracy=tight (Capacitors)

RESaccuracy=tight (Resistors)

To use these different criteria, add the following statement to the Interconnect command:

Interconnect Adapt=(0.05,0.05)
APaccuracy = tight RESaccuracy=fair

To illustrate this, we have made a 3D process simulation of an inverter using CLEVER (Figure 2). A SPICE netlist (Figure 3), including active devices and parasitics, was extracted from the simulation using our 3D field solver. We then created a SPICE input deck (Figure 4) that simulated a ring oscillator using the netlist in Figure 3.

Figure 2. 3D structure of an inverter.

Figure 3. Spice netlist

Figure 4. Spice input deck.


Table 1 shows the SPICE response, memory requirements, and simulation times of a SPICE-simulated ring oscillator based on the defined accuracy parameters. The results indicate the computed SPICE delay, as simulated with the parasitic netlist extracted with CLEVER, does not vary widely in this example. However, both simulation time and memory requirements increase significantly between criteria of “veryloose” and “verytight.” Gains can be as high as a factor of 17 for simulation time, and a factor of 8 for memory, with a SPICE result differential of less than 2%.

SPICE delay
per stage
Very Tight 1718 s 263 Mb 46 ps
Tight 955 s 162 MB 45.89 ps
Fair 536 s 103 MB 45.78 ps
Loose 202 s 49 MB 45.52 ps
Very Loose 105 s 33 MB 45.36 ps

Table 1. Ring oscillator spice simulation results for different accuracy tolerances.

CLEVER can also apply any accuracy criterion over a single node. This is essential if a node is critical in the layout design. For example, if the parasitic elements over a node called ‘VDD’ are critical for a design, one can perform this simulation:

Interconnect Capacitance adapt=0.05
Interconnect Capacitance contact=”VDD”

The first statement above sets the accuracy criterion to 5% over all the nodes on the circuit, while the second statement sets accuracy criterion for the specific “VDD node” to 2%. In Figure 5, the mesh is adapted and refined automatically within the desired 5% accuracy. In Figure 6, where the desired accuracy criterion is 2%, the “VDD node” electrode on the left-hand side of the picture is meshed considerably finer than in the default simulation. Since only parts of the structure are computed with maximum accuracy, computing time is reduced. Table 2 shows that only the capacitors attached to the “VDD node” are affected by the change in accuracy criteria.

Figure 5. Default mesh (5% accuracy required).

C1 in gnd 8.48701e-16
C2 in out 1.47932e-15
C3 in vdd 8.46291e-16
C4 gnd out 4.54491e-16
C5 gnd vdd 3.50237e-17
C6 out vdd 4.56666e-16
C1 in gnd 8.48701e-16
C2 in out 1.47932e-15
C3 in vdd 8.77543e-16
C4 gnd out 4.54491e-16
C5 gnd vdd 4.55274e-17
C6 out vdd 4.9166e-16
Default 5% accuracy Default 5% accuracy + 2% over VDD node

Table 2. Variations in extracted capacitances
when the tolerances are changed.

CLEVER also includes a robust netlist reduction feature. In the 3D structure shown in Figure 2, the gates are accessed from the two upper metallization layers. Access resistances must be correctly extracted and the connectivity must be consistent. Since very small values of capacitance and resistance do not dramatically affect the SPICE simulation, two new switches have been introduced that specify both minimum values to be written in the SPICE netlist:

Interconnect minRES=0.01
minCAP=5E-18 Adapt = (0.05 , 0.05)

In this case, CLEVER performs network reduction at the physical level of the parasitic calculation. This eliminates direct reduction of the SPICE netlist, which could inadvertently introduce “dangling nodes.” Table 3 shows a comparison between netlists with standard and reduced parasitic extraction. In the reduced netlist, resistors have been artificially limited to values above 1 Ohm. Despite this threshold, lower values are still present in the reduced netlist in order to make sure that no dangling nodes are introduced.

R1 aux1 gate1 49.9053
R2 aux1 i 1.11292
R3 aux1 gate0 47.805
R4 i H1 2.17512
R5 aux2 H4 0.0457013
R6 aux2 cont3 0.437311
R7 aux2 aux3 0.0556269
R8 aux3 cont5 0.4479
R9 aux3 vdd! 0.0132343
R10 aux4 aux5 0.0966024
R11 aux4 H3 0.0947903
R12 aux4 cont2 0.592232
R13 zn aux5 0.00418292
R14 aux5 cont4 0.438251
R15 aux6 aux7 0.0682582
R16 aux6 H2 0.0454305
R17 aux6 cont0 0.42867
R18 aux7 cont1 0.447886
R19 aux7 gnd! 0.0146793
Full resistors netlist

R1 aux1 gate1 49.9053
R2 aux1 i 1.11292
R3 aux1 gate0 47.805
R4 i H1 2.17512
R5 cont3 H4 0.0457013
R6 cont3 cont5 0.4479
R7 cont3 vdd! 0.0132343
R8 H3 zn 0.0966024
R9 H3 cont2 0.592232
R10 zn cont4 0.438251
R11 H2 cont1 0.0682582
R12 H2 cont0 0.42867
R13 cont1 gnd! 0.0146793
Netlist reduction

Table 3. Comparison between the
full resistor netlist and the
reduced resistor netlist.


CLEVER 3.0.0.R release addresses the increase in complex high-accuracy circuit simulation by bringing greater attention and flexibility to accuracy handling. New Interconnect command parameters help the user to define detailed accuracy parameters, and then to adjust the emphasis over the numerical schema in order to tighten or loosen convergence criteria. Memory requirements and simulation time are lowered considerably, allowing the input of larger, more complex structures.

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