Parasitic Extraction Today:

A Comparison Between Classical Full Chip Extraction and Field Solver Extraction


With current technologies, parasitic effects must be taken into account in the first phase of IC design development. So, Layout Parasitic Extraction (LPE) is today a very important step before circuit simulation and tape out.

This article will present two different ways to extract parasitics from an IC design: first using a full chip extraction tool HIPEX-RC based on geometrical information, then using a field solver based extraction tool CLEVER.

The HIPEX-RC and CLEVER core features will be detailed in the first part. We will then use these two different tools to characterize inverters and see the consequences on parasitics extraction accuracy.

The goal of this article is not to give exhaustive information about the software but to highlight the differences in regards to capacitance extraction.


LPE Based on Geometrical Information: HIPEX-RC

HIPEX is based on a geometrical engine to detect and extract parasitic capacitance and resistance. It is able to extract three groups of capacitance described below :

  • The Overlap Capacitance: It is detected when two different layers overlap. The Capacitance between the two plates is extracted

Figure 1. Overlap Capacitance.


  • The Lateral Capacitance: It is detected when two identical layers are in the same level. The capacitance between the 2 edges is extracted

Figure 2. Lateral Capacitance.

  • The Fringe Capacitance: It is detected when two different layers overlap (like Overlap Capacitance). The Capacitance between the edge of first layer and the plate is extracted

Figure 3. Fringe Capacitance

We can note that two events lead to a capacitance extraction in HIPEX-RC:

  • Overlap of different layers (overlap and fringe capacitance in Figure 1 and 3)
  • Face to face of two identical layers (lateral capacitance in Figure 2)

The capacitances are extracted only if the two layers involved are inside a vicinity zone. It means that if the distance between the two layers is outside the vicinity zone, the capacitance will not be extracted.

Once a capacitance is detected the geometrical engine will take into account the environment as it may influence the value extracted.

See Figure 4 with an example of an overlap capacitance defined between the two black layers. The perturbations involved by the shading layers are represented in gray.

Figure 4. Overlap capacitance: 3 different zones

HIPEX-RC detects three different zones (zone 1,2 and detects three different zones (zone 1,2 and 3 from Figure 4) where different geometrical parameters will be extracted.

Indeed, HIPEX-RC returns all the geometrical parameters from the structure: area overlap, perimeter, distance between 2 layers... Then three different strategies can be used:

  • Let HIPEX-RC apply its built-in formula
  • Create a user-defined formula as a function of these geometrical parameters
  • Create a Table look-up model

With this method, HIPEX-RC is able to treat large full chips with a minimum of CPU time.


LPE Based on Field Solver: CLEVER

CLEVER is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions.

A 3D-process simulator is used to reproduce the topography realistically (Figure 5).


Figure 5. 3D structure.

The process steps are driven from existing masks in standard GDSII data format from the current design. The 3D grid re-meshing required for each of the steps is generated totally automatically and requires no user input (Figure 6).


Figure 6. 3D structure Mesh.


Finally a 3D-field solver is used to calculate capacitances and resistances (Figure 7).

Figure 7. Potential calculated from Laplace’s equation.

This approach is well known to be the most accurate when compared to measurements [2] as there is no more capacitance detection based on pattern. So they all will be extracted with their real environment and perturbation.
But this way of working based on high computing method leads to longer simulation and restricted layout size.


CASE STUDY: A Simple Inverter

Significant difference on capacitance extraction may be noticed on simple design between results coming from HIPEX-RC and CLEVER. The comparison will be based on two measured targets:

  • The delay from the inverter (propagation time between IN and OUT)
  • The capacitances between the nodes IN, OUT and Ground

First consider the following inverter (Figure 8).

Figure 8. Inverter_1.

Using the extracted parasitic netlist back annotated onto the netlist allows a SPICE simulator to measure the delay between IN and OUT. Similar results are obtained Table 1).

Delay in/out (ns)

Table 1: Simulation result with inverter_1.

Consider now the following design with another inverter. Input and output signals are now interlaced. See Figure 9 and 10 for the plan and 3D view.

Figure 9. Inverter_2 with interlaced input and output.


Figure 10. 3D View of the inverter_2.



The simulated delay with parasitics are now shown in Table 2. CLEVER gives different results as compared to HIPEX-RC.

Delay in/out (ns)
Cout_gnd (FF)
Cin_gnd (FF)
Cin_out (FF)

Table 2. Simulation/extraction result with inverter_1.


If we refer to Table 2 we can give two explanations. They will be based on the vertical cut view below which shows more in detail the input and output signals interlaced (Figure 11).


Figure 11. IN and OUT interlaced (inverter_2).


First, the Cout_gnd capacitance is higher with the HIPEX-RC extraction than with the CLEVER one. As previously explained the field solver extraction takes into account all the perturbation generated by other conductors. In this situation, the IN signal acts as a perturbation between the OUT and GND conductors. HIPEX-RC is not able to detect it because there is no overlap between the OUT and IN signals. HIPEX-RC analyses the capacitance between OUT and GND as if the layout looks like the one shown in Figure 12.


Figure 12. GND and OUT seen by HIPEX-RC.

As a result the Cout_gnd capacitance is overestimated by HIPEX-RC mainly due the two fringe capacitances.

However it doesn’t explain why the parasitic netlist extracted by HIPEX-RC gives a delay smaller as compared to CLEVER. Another phenomena with a higher influence than the previous one will clarify the situation.

We can note an important difference between the Cin_out capacitance extracted from HIPEX-RC and CLEVER. In the area represented in Figure 11, there is no overlap between IN and OUT signals and there are on different level (IN is in Poly and OUT in Metal1). If we refer to what was written about capacitance detection with HIPEX-RC, nothing will be detected in this area. This explains why the capacitance between IN and OUT is so low (a small overlap is present in another part not represented in the cut view from the Figure 11). This underestimation leads to a delay slightly shorter with HIPEX-RC.



From an accuracy point of view, only a field solver can give good results independently of the layout used. But another criterion must be taken into account: the extraction time. On a structure similar to the previous one repeated thirty-one times to obtain a ring oscillator, the extraction time can vary from one minute with HIPEX-RC to thirty minutes with a field solver like CLEVER.

This article, based on a concrete example, shows that parasitic extraction can be done in several ways. Each method should be used according to the size of the layout, the accuracy level expected and the inputs we have.

However the perspective is to mix these two methods instead of choosing between them.



  1. Silvaco,”HIPEX-Hierarchical Layout Parameter and Parasitic Extractor”, Simulation Standard, March 2003, applications/archive/2003/mar2003/mar03_a1/mar03_a1.html.
  2. B. FROMENT, et al., “New interconnect characterization method for multilevel metal CMOS processes”, ITTC may 1999. 12. GND and OUT seen by HIPEX-RC.

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