Accounting for Shallow-Trench-Isolation (STI) Effects in BSIM4 and HiSIM MOSFET Models


1. Introduction

Semiconductor devices are continuously improved with regard to intrinsic characteristics, as well as reduced geometries. Among all requirements, there is a need for an efficient device isolation technique as CMOS technologies are scaled down below the 0.25µm generation. Shallow Trench Isolation (STI) has become an essential isolation scheme as a replacement for LOCal Oxydation of Silicon (LOCOS). It allows reaching a higher packing density, tighter design rules, lower parasitics and higher yields. However, the basic STI process sequence involves several sources of mechanical strain, which can significantly increase the stress levels in the enclosed silicon area (Figure 1). It was shown that this stress in turn influences junction leakage but also MOS electrical characteristics. There are several ways to account for the effect of STI-induced stress in standard compact models. The purpose of this article is to present two different approaches developed by the universities of Berkeley and Hiroshima. In both cases, new equations were derived and new parameters have been introduced in the latest versions of BSIM4 and HiSIM compact models. These new versions are currently supported by Silvaco SmartSpice/UTMOST softwares.

Figure 1. Mechanical stress induced by STI process.


2. HiSIM STI Model Equations

HiSIM is a MOSFET model developped by Hiroshima University, started in 2001. The equations for the STI effect were added in version 1.1 and account for two major STI effects experimentally observed on I-V characteristics:

a “double hump” in the Id/Vg characteristic (sub-threshold region),

a lower threshold voltage value.

The edge of the trench has an influence on the electric field. The impurity concentration and the oxyde thickness are different from those at the middle of the width. Therefore, a modified surface potential is computed. Since the threshold voltage for the corresponding leakage current is different from the threshold voltage of the main current, the STI effects can be observed only in the sub-threshold region.

The local modified surface potential is computed using the expression shown in equation 1.


Equation 1.


These equations are based on the assumption that the current in the subthreshold region is mainly due to diffusion. The carrier concentration, QN,STI, is calculated analytically using the Poisson equation, with a dedicated substrate impurity concentration NSTI. The WVTHSC parameter is used to discriminate the short-channel threshold characteristics of the edge from the intrinsic part.

The final equation is shown in equation 2.

Equation 2.


The WSTI parameter represents the width of the high-field region.

An example of the I-V characteristics is shown on Figure 2. It is important to note that unrealistic parameter values are used to make the “double hump” and the lower threshold voltage visible. For most practical situations, the effect on I-V characteristic is not so important and may be negligeable with optimized STI processes.


Figure 2. STI-induced stress effect on Id-Vg characteristics.


3. BSIM4 STI Model Equations

The approach chosen by the University of Berkeley is based on the observation that the mechanical stress induced by STI makes MOSFET performance depend on the active area size, as well as the location of the device in the active area. The effect of stress on mobility and saturation velocity was experimentally demonstrated. A phenomenological model was derived and introduced in BSIM4v3.0 to consider the influence of stress on mobility, velocity saturation, threshold voltage, body effect and DIBL effect.

In the Silvaco implementation of BSIM4, several stress effect models can be invoked by specifying the model parameter STIMOD. This selector was not supported in the original Berkeley release of BSIM4v3.0. As STI effect is turned off by default, it is supported for all versions of BSIM4.

  • STIMOD=0

Stress effect turned off.

  • STIMOD=1 (Berkeley model introduced in BSIM4.3.0 beta of December 2002) If instance parameters SA, SB are set to positive values with NF=1 or if SA, SB, SD are all set to positive values with NF>1 and the model parameter SK0 is also set to a positive value, the mobility U0(T)and the carrier velocity VSAT(T) account for changes due to stress effect and are expressed as shown in Equation 3.

Equation 3.


  • STIMOD=2 (TSMC model for irregular LOD devices) This model corresponds to the Berkeley model (STIMOD=3) with different expressions for the intermediate variables Inv_sa and Inv_sb. These latter ones are computed as functions of instance parameters SA1...SA10, SB1...SB10 and SW1...SW10 to account for irregular LOD devices. NF must be unspecified or set to 1 to allow stress effect computation if STIMOD=2 is invoked. (Equation 4.)

Equation 4.


  • STIMOD=3 (Berkeley model for multi-finger devices) This model was introduced by Berkeley in the final release of BSIM4.3.0 of May 9th 2003. It considers the influence of stress on mobility, velocity saturation, threshold voltage, body effect and DIBL effect by modifying the parameters shown in Equation 5.

Equation 5.


The TSMC model was developed to account for devices with irregular oxide definition (Figure 3). Berkeley models must be used for multi-finger devices (Figure 4). If only SA (or SA1) and SB (or SB1) are specified with NF=1, STIMOD=2 and STIMOD=3 models are equivalent.

Figure 3. Irregualr LOD device geometry parameters.

Figure 4. Multi-fingers device geometry parameters.



4. Conclusion

BSIM4 and HiSIM offer two different ways to account for the same physical phenomenom. The HiSIM model is physically-based but requires the computation of extra bias-dependent equations, which may be time-consuming when running large circuits. The Berkeley model is phenomenological and has no impact on simulation time because only some parameters are modified during pre-processing calculations (temperature- and geometry-dependent parameters). The accuracy of both models may vary significantly with STI processes.

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