Behavioral Modeling and Simulation in the Scholar Schematic Environment


This article focusses on the use of Silvaco International’s schematic capture and editing tool Scholar combined with Verilog A. Verilog A is a standard language used for behavioral level modeling. Verilog A combined with Scholar forms a powerful tool capable of running both schematics with Verilog A modules and mixed Verilog A and physical model simulations. Verilog A may also be used in an environment for compact model development but primarily it is used to reduce schematics of significant amounts of transistors into efficient maintainable and changeable blocks which can be instantiated on any level of a design.

Silvaco’s Scholar is the entry point for the Analog Express design environment. The Scholar schematic is netlisted for SmartSpice and tightly integrated for running simulations concurrent with the schematic. Scholar handles behavioral simulations in two ways:

  • Use of analog behavioral SPICE element (A device)
  • Verilog-A

The analog behavioral element (A device) is a two-port device capable of describing a voltage across or current through the pins of the device. These currents and voltages may be logical expressions or user-defined functions. Listed below is an example of an A device which is defined here as a temperature dependent linear resistor connected between nodes A and D:

.TEMP = 100
+ TNOM = 25
+ TC1 = 0.02 TC2 = 0.03
+ DT = ‘TEMP - TNOM’
AR A D I = (V(A) - V(D)) / (RNOM * (1. + TC1 * DT + TC2 * DT^2)

The current through this device is a function based on the temperature coefficients and voltage difference across the terminals of the device. This is an adequate behavioral modeling for simple devices. However, more complex devices need a language suited for producing behavioral models capable of reducing hundreds to thousands of transistors to single or multiple behavioral blocks. In this case, the Verilog-A language built into SmartSpice provides a powerful solution to achieve accuracy and gain speed.


Advantages of the Schematic Driven Environment

  • Verilog-A modules may be used inside a multilevel design hierarchy by instantiating Child files inside a Parent module
  • Schematic environment provides capture of mixed Verilog-A and physics –based models for simulation
  • Schematic symbols may be mapped to analog primitives -- SPICE devices, model cards or subcircuits that can be instantiated from a Verilog-A module
  • In the Scholar+Verilog-A environment, top-down approach design methodology is easily utilized which produces requirements for deriving the individual circuit blocks


How to Implement Verilog-A in Scholar

To use the environment for schematic, simulation, Verilog-A, and postprocessing, the following licenses are required:

  • Scholar
  • SmartSpice
  • Verilog-A
  • SmartView

The following example is for an RSFF simulation using Verilog-A:

1. Create a *.va file. This is file containing the Verilog-A module(s). In this case, a file is created with the RSFF module definition. (Figure 1)

Figure 1. file containing Verilog-A module.

2. Create a symbol in Scholar to reference the file from the first step. (Figure 2)

Figure 2. RSFF.body symbol file.

3. Define the SmartSpice string for the symbol. (Figure 3) This string is defined as follows

  • Reference designator YVLGRSFF@PATH which defines each instance as type YVLG (Verilog-A device).
  • The pins are defined in the order which they should netlist, each pin name beginning with the % character in the string
  • Finally, the model name for the device, RS_VLG

Figure 3. Defining SmartSpice string for the RSFF.body symbol.

4. Define the model card for the Verilog-A module in the control file (*.ctr). In this example, the model RS_VLG is linked to the V_rsff module in the file (Figure 4)

Figure 4. Defining the .MODEL card in the control file.

5. Create the schematic and instantiate the Verilog-A symbol created in step (2) (Figure 5)

Figure 5. Create schematic to simulate the module.

6. Simulate the schematic and view the results (Figure 6)

Figure 6. Simulation of RSFF Verilog-A module and results.


The Scholar schematic editor is a tool capable of driving simulations for both physics-based device models and behavioral level modeling using Verilog-A. Top-down design saves time and drives the design of individual circuit-level blocks. With the scholar interface, symbols may be readily changed in and out, swapping the transistor level designs and the Verilog-A behavioral designs, providing designers with the means to reduce simulation time for portions of the design and overlay results on the same plots.

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