A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

Santanu Mahapatra, Adrian Mihai Ionescu, Electronics Laboratory (LEG), Institute of Microelectronics and Microsystems (IMM), Swiss Federal Institute ofTechnology Lausanne (EPFL), ELB-Ecublens, Lausanne, CH 1015, Switzerland
Kaustav Banerjee, Department of Electrical & Computer Engineering, University of California Santa Barbara, CA 93106-9560, USA
Florent Pegeon, Silvaco Data Systems, 55 rue Blaise Pascal, ZIRST II, 38330 Montbonnot St. Martin, Grenoble, France
Email: Santanu.Mahapatra@epfl.ch, kaustav@ece.ucsb.edu, florent.pegeon@silvaco.com, Adrian.Ionescu@epfl.ch


This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. Circuit level co-simulations are successfully performed by implementing the SET analytical model in Analog Hardware Description Language (AHDL) of a professional circuit simulator SmartSpice. Validation at device and circuit level is carried out by Monte-Carlo simulations. Some novel functionality hybrid CMOS-SET circuit characteristics: (i) SET neuron (ii) Multiple valued logic circuit and (iii) a new Negative Differential Resistance (NDR) circuit, are also predicted by the proposed SET model and analyzed using the new hybrid simulator.


I. Introduction

Although scaling of CMOS technology has been predicted to continue for another decade, novel technological solutions are required to overcome many limitations of the CMOS [1]. Several nanotechnologies are rapidly evolving, but at this point it seems unlikely that any of them can completely replace CMOS [2]. However, co-design of CMOS and some suitable nanotechnology seems more plausible [3]. In fact, in the near future, it seems highly probable that CMOS technology will need to share its present domination on modern ICs with fundamentally new nanotechnologies such as Single Electron Transistors (SET) that use a few electrons [4]. It appears that CMOS and SETs are rather complementary: SET is the campaigner of low-power consumption [5,6] and of new functionality while CMOS has advantages like high-speed driving and voltage gain, which can compensate exactly for SET’s intrinsic drawbacks. Therefore, although a complete replacement of CMOS by SETs is highly unlikely in the near future, it is also true that combining SET and CMOS can bring out new functionalities [7-8], which are un-mirrored in pure CMOS technology.

It is well known that Computer Aided Design (CAD) and simulation of electron devices and circuits (using tools like SPICE) are one of the key factors contributing to the success of the CMOS technology. Therefore, a successful implementation of SET as a candidate for hybrid CMOS-nano VLSI also demands accurate modeling and simulation of CMOS-SET devices and circuits. Hence, a suitable simulation framework for exploration of hybrid CMOS-SET circuit architectures is highly desirable. In this paper we introduce a new CAD framework for co-simulation of hybrid CMOS-SET circuits. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. The SET model is validated using Monte Carlo simulations, which are typically used as a benchmark for accurate SET- device and circuit level simulations. Some novel functionality CMOS-SET circuit architectures are analyzed using the new hybrid simulator.

A schematic of a SET, which consists of a tiny conductive island, two high resistive (>26k) tunnel junctions, and an opaque gate is shown in Figure 1. It is worth noting that the operation of the SET devices is based on the Coulomb Blockade phenomenon [9], which is quite unique compared to the principle of operation of MOS transistors. By exploiting this particular Coulomb Blockade phenomenon, several niche applications of SET devices have been demonstrated in logic circuits (inverter, logic gates etc.)[5,6,10], analog circuits (neuron cell, negative differential circuit [8,11]) and in mixed signal circuits (quantizer [7]) regime.


Figure 1. Schematic of a SET. Here CG is the gate capacitance,
CG2 is the optional second gate capacitance,
CTD and CTS are the drain and source tunnel
junction capacitances, respectively, and RD and RS
are drain and source tunnel junction resistances, respectively.


II. Set Simulation: An Overview

Monte Carlo (MC) simulation method is the most popular approach that is employed to simulate single electron devices and circuits. Some of the widely used single-electron MC simulators are SIMON [9], MOSES [12] and KOSEC [13]. Some efforts have also been made to simulate single electron device and circuit characteristics by Master Equation Method (e.g.: SETTRANS [14] ). It should be noted that:

  1. These methods calculate single electron device and circuit characteristics based on “Orthodox Theory” [9] (i.e., manipulating electron energy with the help of complex Fermi-Dirac distribution and Fermi’s golden rule) instead of using any analytical model of SET.
  2. These simulators are developed in order to simulate generalized single electron devices (where the charging energy of the island is determined not only by the drain, source and gate capacitances associated with it but also other capacitances associated with other islands in the same circuit) and it is quite impossible to find an analytical model for single electron devices. [Note: SET (where the charging energy of the island is determined solely by the drain, source and gate capacitances associated with it) is a special case of generalized Single Electron Devices].


III. Chalanges of Set-CMOS Co-Simulation

Some previous works have addressed [15] the hybrid SET-CMOS simulation based on background MC or Master equation simulation of SET devices combined with conventional analytical model based on SPICE simulation for MOSFETs. However, the major disadvantage of these approaches is time-consuming computation (especially for the calculation of transient response, current sources and resistances), and concrete limitations for more complex circuits.

It should also be noted that simulation of SET devices are not as straightforward as CMOS devices. Some architecture, which is commonly used in CMOS technology, may be ‘forbidden’ in SET circuits. One such example is shown in Figure 2. The architecture in Figure 2(a) is commonly used in CMOS (e.g. Differential Amplifier) however a similar SET prototype [Figure 2(b)] may create instability in the circuit (and convergence problems in simulation) as the periodic IDS-VGS characteristics of a SET offer several possible values of VGS is for a certain value of IBIAS [Figure 2(c)]. We’ll see in §VIII.III how we can exploit such an apparent limitation to provide NDR characteristics in a hybrid CMOS-SET IC.


Figure 2. (a) A current bias MOSFET with a floating gate
(b) corresponding SET prototype (c) Different possible
value of the gate voltage for in (b) for a fixed current bias.


Apart from MC and Master Equation method, “Macro Modeling” technique [16] has also been employed in order to simulate SET devices and circuits. Although this technique is SPICE compatible and useful for co-simulation with MOS, its non-physical (or, empirical) nature makes it an inconvenient tool for practical SETCMOS hybrid IC design. Therefore, a successful implementation of SET as a candidate for post-CMOS VLSI demands an accurate analytical SET model instead of Monte Carlo (MC) simulation, Master Equation Method or macro modeling.

Recently, analytical models MIB [5,17] and Uchida et al.[18] have been reported, which appear to be extremely exciting for practical IC design. These models are physically based, and are easily used in conventional SPICE for the co-simulation with CMOS devices.

The model reported by Uchida et al.[18] is adequately accurate for high temperatures, however it is only applicable to the single gate resistively symmetric device and it cannot explain the background charge effect, which is significant for SET operations. On the other hand MIB, which is applicable to single/multiple-gate symmetric/asymmetric devices, can explain the crucial background charge effect. However it is not as accurate as [18] for high temperatures due to its semi-empirical modeling of the temperature effect. One point to note is that, both of these models are developed under the basic assumption of |VDS| < e/C (where e is the elementary charge and CS is the total capacitance of the SET island with respect to ground), which is quite practical for digital circuits (as the SET loses its Coulomb Blockade region and hence the digital switching property when |VDS| > e/C). However, for the analog application of SET [8], one needs a model which is applicable to any value of VDS. This is due to the fact that:

(i) In a current biased SET (which is a common building block of analog SET circuits) the |VDS| could be more than e/CS .

(ii) In CMOS-SET hybrid architecture MOSFET biases may impose |VDS|>e/CS to operate the SET.

In this work, we have modified the MIB model in order to extend its validity over |VDS| > e/CS specifically for analog circuit operation. Moreover, we have modeled the temperature (T) effect physically so that MIB can predict the device behavior accurately at higher temperatures. In order to exploit the proposed model for SET-CMOS hybrid IC design, MIB has been implemented by the Verilog-A interface (which is one type of Analog Hardware Description Language) in the professional circuit simulator SmartSpice [19]. Using SmartSpice different simulations have been performed in SET device and circuit level for different benchmark circuits and good agreement with MC simulation has been observed.


IV. Analytical Models for Set: MIB

SET analytical model MIB, which is founded on the “orthodox theory of single electron tunneling” [9] (i.e., charge is discrete but energy is continuous, tunnel junction resistance is more than the quantum resistance ~ 26K etc.), is based on a practical assumption that the interconnect capacitance associated with the gate, source and drain terminals is much larger than the device capacitances, this ensures the total capacitance of the island with respect to ground is equal to the summation of gate and source/drain tunnel capacitances i.e.,

In this way the SET characteristics are independent of the capacitances of neighboring devices and are only dependent upon the nodal voltages of source, gate and drain terminals.

In this work, the following improvements are made over the earlier version [5] of MIB:

  • MIB is extended for | VDS | ≤ 1.5e/C for resistively symmetric device and | VDS | ≤ 1.2e/C for resistively asymmetric device, which is essential for analog applications of SET. It is found that for | VDS| > 1.5e/C, variation of IDS with VGS becomes too small to exploit in any circuit application
  • The temperature effect is modeled physically which enables the temperature range of MIB to be extended
  • Another key result, the Subthreshold Slope can be estimated analytically
    The algorithm for the calculation of drain current in MIB model (Figure 3) can be briefly discussed as follows:

Based on the external bias voltages (VDS, VGS, VGS2) the initial (before any electron tunneling has occurred) island potential ( Visland ) can be calculated as:

where n is a real number representing the background charge. Now, according to the “orthodox theory”, when the potential difference between island-and-source or drain-and-island becomes larger than V [= e/(2C)], one electron tunnels-in or tunnels-out from the source to island or island to drain and as a result Visland decreases (for tunnel-in) or increases (for tunnel-out) by an amount of 2VS. However, if the potential difference between island-and source or drain-and-island becomes less than VS no electron tunneling happens and the device enters into the Coulomb Blockade region. The first pair of ‘while’ statements in the MIB algorithm (Figure 3) is used to modify the initial island potential ( Visland ) in order to capture the periodic Coulomb Blockade oscillation characteristics of SET. Based on this modified value of Visland , the drain current (IDS) is formulated as

Here IS and ID are the electron-tunneling current from source-to-island and island-to-drain respectively which can be expressed as

where VT (= kBT/e, kB is the Boltzmann’s constant) is the thermal voltage. It should be noted that the expressions of IS and ID are purely based on the “orthodox theory” of single tunneling and completely different from the older version of MIB (where the temperature effect was modeled empirically). In order to include the |VDS| > e/C effect, in this work, we have added an extra component to the main component of the drain current as shown in Figure 3.

Figure 3. Flowchart for the MIB analytical Model.


It is worth noting that all the model parameters of MIB are physical: (i) drain and source tunnelling capacitances (CTD and CTS), (ii) first and second gate capacitances (CG1 and CG2), (iii) drain and source tunnel junction resistances (RD and RS), and the background charge (n).


V. Implementation of MIB in Verilog-A

Verilog-A [19] is a “high level hardware description language” of analog systems by which one can mix SmartSpice device models (such as BSIM [19], EKV [19] etc.) and Verilog-A modules in the same netlist. In this work, we have implemented the MIB model for SET devices in Verilog-A language and then simulated them with the SmartSpice simulation kernel as shown in Figure 4. In this way, we can use the MIB analytical model to co-simulate the SET device with any other solid-state device (MOS, BJT etc.) instead of using the time consuming MC technique [9,12,15]).


Figure 4. (a) Working principle of Verilog-A in SmartSpice
(b) partial architecture of Verilog-A SET module.

In the present work one can use various levels of complexity of MIB which are listed as:

LEVEL1: T = 0, |VDS| ≤ e/ C (for hand calculation)

LEVEL2: T < e2/(20kBC ); |VDS| ≤ e/C (for digital operation)

LEVEL3: T < e2/(20kBC); |VDS| ≤ 1.5e/C for symmetric and |VDS| ≤ 1.2e/CS for asymmetric SET. (analog purpose)

It should be noted that the SET module is implemented with default values of model parameters (gate capacitances, tunnel junction capacitances and resistances, and back ground charge),which can be changed easily through the MODEL CARD in the SPICE netlist.


VI. MIB Model Verification

The proposed model (embedded in SmartSpice) has been verified against the simulated data from the widely accepted Monte Carlo simulator SIMON [9]. Figure 5(a) reveals the validity of our model for a wide range (even more than e/CS) of values of VDS, which is important for SET analog operation. Figure 5(b) demonstrates the accuracy of our model for an asymmetric SET. It should be noted that by introducing asymmetry one could reduce the static power dissipation in SET logic while keeping the dynamic power dissipation and propagation delay almost constant [5]. However the importance of resistively asymmetric current biased SET in analog applications has not yet been demonstrated. Figure 5(c) exhibits the validity of the MIB model for a wide range of temperatures up to T = e2/(20kBC), Note: According to Kirihara et al.[20] maximum temperature for stable SET logic operation is e2/(40kBC). From our new model the subthreshold slope (S) of the SET is found to be S = dVGS/dlog10IDS = (CkBT)/(0.434eCG).


Figure 5: Verification of MIB model for (a) symmetric
SET device with CG = 2aF, CTD = CTS = 1aF and
RD = RS = 1M. Here symbols denote Monte Carlo
simulation (SIMON) and solid line represents
MIB LEVEL3 and dotted line represents
MIB LEVEL2 (without |VDS|>e/C correction).
(b) asymmetric device with CG = 2aF, CTD = 1.5 aF,
CTS = 0.5aF and RD
= 1M and RS = 5M
(c) effect of temperature on the device characteristics.


VII. Pure Set Logic Circuit Simulation

Static and transient responses of a SET inverter cell are successfully predicted [Figure 6] by SmartSpice simulation. Comparison and good agreement with MC simulation reveals the accuracy of our SPICE simulation in both static and dynamic regimes as given in Figure 6(a) & (b). One should note that a SET inverter is different from a typical CMOS inverter in the following respects:

(i) In a SET inverter the two transistors are completely identical to each other (in contrast with a CMOS inverter where we have one p-MOS and one n-MOS).

(ii) Unlike the CMOS counterpart, the SET inverter does not offer a constant voltage level when the output is in logic high or low.

(iii) The gain of a SET inverter is quite low compared to a CMOS inverter and it is determined by CG/CT ratio.

(iv) In contrast to the CMOS inverter, power dissipation in SET logic is dominated by static power dissipation.

A detailed analysis of the SET inverter along with the effect of background charge, device asymmetry and temperature on the inverter characteristics could be found in [5].

Figure 6. SET-inverter (a) static and (b) transient characteristics
for different values of CG/CT (solid line = SmartSpice and
symbol = SIMON). T1 and T2 are identical with
RD = RS = 1M, CT = CTD = CTS
and load capacitance
CL = 1fF.
The oscillations in the MC simulation in (b) are
due to the noise in the random number generator.


VIII. Hybrid CMOS-Set IC Simulation

As mentioned previously, a complete substitution of CMOS by single-electronics is highly improbable in the near future, therefore we have to combine SET and CMOS in order to bring out new functionalities. For these reason it is extremely important to develop a simulator, which is able to co-simulate SET devices with CMOS. In the following sections we will discuss three examples of CMOS-SET hybrid IC.


VIII.I. Set Casacade Neurone

Since a powerful signal processor demands a large neural network, therefore, due to the power dissipation and size of the neural chip it is difficult to design an efficient neural network by CMOS technology. However, one can exploit the ultra low power dissipation of SET devices and their nano feature size in order to realize a compact neural device.

The basic building block of a neuron is given in Figure 7. The most challenging part of this neuron cell is to design the activation function block, which is generally expressed by a sigmoidal function as given below

As proposed by M. Goossens [8], the activation function of a basic neuron cell can be implemented by two cascaded current biased SET as presented in Figure 8.
According to Goosens [8], for the proper operation of the circuit, the drain and source tunnel capacitances of the SETs have to be equal (CTD = CTS) and the gate capacitances have to be twice that (CG = CG2 = 2CTD). One point to note is that in order to drive a nA current through the SET one has to bias the MOS transistors in the sub-threshold (weak inversion) region.


Figure 7. Functional block diagram of a neuron.

Figure 8. Basic structure for the realization of the activation
function of a neuron as proposed by Goossens [8].


Using SmartSpice, the static characteristics of the neuron cell [8], have been simulated accurately and good agreement with MC simulation [Figure 9] is shown, this demonstrates the reliability of our physical analytical model. Note: In this figure, MIB model without |VDS| > e/C correction is represented by a dotted line. In the the figure the exhibited inaccuracy with MC simulation for a certain range of input voltage, demonstrates the requirement of a SET model to be valid over 1/2VDS1/2 = e/CS for analog circuit applications.

Figure 9. Characteristics of basic SET-CMOS hybrid neuron cell [5]
(with CG = GG2 = 0.04aF, CTD = CTS = 0.02aF, RD = RS = 1M)
as predicted by SIMON (symbol) and SmartSpice (solid & dotted line).
Note: Ibias is taken to be ideal current source of 50nA for SIMON
simulation and for SmartSpice simulation the MOS current source is designed
in such a way that it can drive the same bias current through the SET.


VIII.II. Multiple Vauled Logic

Multiple-valued logics (MVLs) have potential advantages over binary logics with respect to the number of elements per function and operating speed. Most MVL circuits, fabricated with MOS and bipolar devices, have limited success partially because the devices are inherently single-threshold or single-peak, and are not fully suited for MVL. Inokawa et al.[7] have recently proposed a hybrid SET-CMOS MVL circuit for practical applications (e.g., quantizer for digital communication system). Figure 10(a) shows the schematic of the hybrid MVL circuit [7]. The MOSFET with the fixed bias VGG is used to suppress the variation of drain to source voltage of the SET. The simulated Vin-Vout characteristics of this circuit are demonstrated in Figure 10(b) which shows good resemblance with the measured data as presented in [7].

Figure10. (a) A schematic of the universal literal gate comprising
a SET and a MOSFET [7]. (b) Comparison between measured
and simulated Vin–Vout characteristics of the universal literal
gate at T = 27K. The SET device parameters are
CG = 0.27aF, CTD = CTS = 2.7aF, RD = RS = 200k
and MOS device parameters are W = 12µm, L = 14µm,
tox = 90nm. VGG is set to 1.08V and Vout is hard-limited at 5V.


It is impossible to achieve such characteristics by using a pure conventional SET circuit because the voltage gain of SET circuits is very small.


VIII.III. Hybrid NDR Circuit

A Negative Differential Resistance (NDR) is a resourceful element with a wide variety of circuit applications such as: oscillators, amplifiers, logic cell and memory. Figure 11(a) demonstrates an alternative CMOS-SET architecture of NDR device [21], which is composed of two cross-connected SETs (S1 and S2) and one MOS current mirror. The I-V characteristics of this NDR circuit and the effect of bias current on the circuit behavior are demonstrated in Figure 11(b). The CMOS current source and the first SET (S1) creates a feedback loop that helps to decrease the gate-to-source voltage (VGS) of second SET (S2) for a certain range of increasing input voltage (VIN), and that follows a decrease in the drain current (or the input current, IIN) of S2, which creates the NDR effect. It is found this NDR architecture appears more versatile than the previously reported structure [11] in terms of dynamic range of NDR region, current controllability and drivability, and offers a very effective solution for real implementation of the NDR functionality.

Figure 11. (a) Schematic of CMOS-SET hybrid NDR circuit, where, the interconnect capacitance CINT is much bigger than the SET device capacitances (b) NDR characteristics as simulated by SMARTSPICE (solid line: MIB LEVEL3 and dotted line: MIB LEVEL2) and by MC simulation (by replacing the CMOS current mirror by ideal current source, denoted by symbols) for the SET device parameters CG = 0.2 aF, CTD =CTS = 0.15aF, RD = RS = 1M for S1 and CG = CTD =CTS =0.15aF, RD = RS = 1M for S2. In order to drive nA current through the SET one has to bias the MOS transistors of the current source in the weak inversion or in moderate-inversion region.


It should be noted that similar circuit architecture [22] (cross coupled MOS devices) is also used for oscillator design (in order to provide negative differential resistance) in CMOS technology. In contrast with such cross-connected CMOS architecture, the proposed SET circuit requires an adapted current bias [see IBIAS in Figure 11(a)] to provide NDR behavior.


IX. Conclusion

A CAD framework is presented for the design and analysis of CMOS-SET hybrid circuits. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. The proposed model is implemented in the professional circuit simulator SmartSpice by its Verilog-A interface for the cosimulation with CMOS devices. The model has been validated in both device and circuit level and compared with Monte Carlo simulations. It is worth noting that the proposed MIB model is particularly adapted for both digital and analog hybrid CMOSSET applications. The need and interest of CMOS-SET hybrid IC simulation has been demonstrated for three IC architecture that demonstrate new functionality compared with pure CMOS: (i) SET neuron, (ii) Multiple Valued Logic circuit (iii) new Hybrid NDR circuit.



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