Simulation of Single-Event Effects in FinFETs Using the ATLAS 3D Device Simulator



A great deal of recent industry attention has focused on the use of non-planar multi-gate device structures in future generation MOS devices that feature channel lengths below about 50 nm [1-3]. The devices are based upon silicon-on-insulator (SOI) substrates, and employ three-dimensional (3D) structures that achieve fully depleted operation with near-ideal, sub-threshold slopes. Like their single-gate planar counterparts, these new SOI devices contain isolated channel regions. The transient charge injection from ionizing radiation events, including so-called "single events," can change the body potential of SOI MOSFETS and initiate transient transistor action [4-5]. This article illustrates the use of ATLAS 3D Device simulations to examine the impact of charge injection in these highly scaled 3D device structures.


Device Structure

Fully depleted SOI devices have long been of interest. However, the scalability of the single-gate devices have so far been limited by silicon thickness control, as well as the need for ultra thin silicon and/or buried oxides. Double gate devices, which have a gate on both the top and the bottom of the channel, often overcome these limitations [6], but process integration issues limit the practical implementation of devices with high transistor densities. Two proposed 3D-device structures are each a variation of the double gate device: the FinFET essentially turns the double gate device on its side [1], while the tri-gate device uses a thin gate oxide on three sides of the device, instead of on only two [2]. Both devices use elevated (thicker) source and drain regions, and is contain electrically floating body regions. Figure 1 illustrates the device structure.

Figure 1. 3D device structure such as used
for the FinFET [1] and Tri-Gate [2] devices.
Figure from [3]. (COPYRIGHT IEEE Spectrum).


Device Simulation

In a laboratory simulation, ATLAS 3D Device was used to simulate the impact of single-event charge injection into various regions of a FinFET device. Figure 2 is the simulated device structure as viewed with TonyPlot 3D and TonyPlot 2D. The starting point was the device published by Huang, et al [1]. Device parameters were calibrated based on published physical dimensions with other parameters set to best match the published DC current values for the PMOS device. Appropriate changes were then made in order to create the NMOS device used in these simulations. The drain and source doping is N+ (1x1019 cm-3) and that of the body is P- (1x1016 cm-3). The gate workfunction was set to 4.6 eV in order to achieve a reasonable threshold voltage of about 0.2 volts [7, 8]. The subthreshold DC - IV characteristics (Figure 3) indicate a slope of 64 mV/decade.

Figure 2. Simulated FinFET device. Top: 3D view with some layers not shown. The arrows show the cross section locations, the "X" ‘s show approximate locations for simulated "hits". Bottom left – cross section along the gate; bottom right – cross section along the channel from drain to source.


Figure 3. Simulated DC IV curves for the NMOS device.
The subthreshold slope is 64 mV/decade.

The charge (electron-hole pair) generation is defined using the singleeventupset statement of ATLAS 3D Device [9]. The statement used for these simulations is (where the z-value of the entry and exit coordinates were varied for the different hit locations):

singleeventupset entry="0.1,0.0,0.2" \
exit="0.1,0.05,0.2" radius=0.05 \
density=1.e18 t0=4.e-12 tc=2.e-12

Two things worth noting:

  1. the scale of the pulse’s temporal profile is on the order of the carrier, which is the transit time across a biased junction (i.e. ~ 10 ps)
  2. the spatial profile of this pulse would cause truncations of the generation region by the device active region physical limits in the body, as well as in some portions of the drain/source regions


Simulation Results

The FinFET device was biased with the drain voltage at 1.5V, and the gate and source voltages at 0V. In each case, a simulation was performed at various locations for the center of the charge injection track, perpendicular to the wafer surface. The axis of the hit location was simulated for the center of the body region, and for three locations in each in the drain and source regions. (Denoted by the X’s in Figure 2, top).


Case 1: Body Hit

After injection into the body region, a fast pulse is first observed in both the drain and source current (Figure 4). This represents the excess electrons created in the body as they cross the body-drain and body-source junction. The net-induced photocurrent is represented by the sum of the two current pulses (also plotted). Excess holes trapped in the potential well of the n-p-n structure raise the potential of the body region causing the body-source junction to become forward biased (Figure 5) and initiating transistor action. This accounts for the second, longer pulse in Figure 4. While the peak value of the second pulse is less than the first, the characteristic time scale is much longer (nanoseconds compared to picoseconds), and the associated charge (integral of the current) is greater than 50 times that of the initially deposited charge.

Figure 4. Drain and source currents for the hit to the body region.
The insert shows a zoomed-in view of the initial time response due to the injected charge.


Figure 5. Potential distribution – evolution over time showing the body potential increase due to the charge injection. Plots are shown at times: pre-strike (b4), 4ps, 50ps, 200ps, 400ps, 600ps, and 0.1us.


Case 2: Drain and Source Hits

Generally for planar single-gate SOI devices of past and current generation devices (> 0.13 um), injection into the body is believed to result in the most pronounced device response since it most efficiently initiates parasitic bipolar action. There has been some discussion about hits to the drain region also contributing [10] to device response. In the present simulated devices, the dimensions of the drain and source regions are comparable to the radial dimensions of the simulated charge track. Simulations were performed with the center of the track at three different locations within the drain and within the source relative to the body silicon region: at 0.3 um, 0.2 um, and 0.1 um away from the thin body region edge (Figure 2, top). The resulting drain currents for each case are plotted in Figure 6. The same trends are observed for both drain and source with the collection efficiency being somewhat less on the source side due to the lower junction bias.

In both cases, some holes generated in the drain (source) region are able to drift and diffuse to the body junction. The initial fast rise is carriers that are in and near the high field region of the junction, while the longer tale is dominated by diffusion to the junction. For a doping of 1019cm-2 in the drain, the minority carrier lifetime is on the order of 50 ps, and the diffusion length on the order of 0.35 um. It is for this reason that the initial current decreases as the hit location is moved away from the drain-body junctions from 0.1 um to 0.3 um.

Comparing the results from the drain/source regions (Figure 6, left) to that of the body (Figure 4), the former produces a comparable (or larger) device response. This is due to the small device dimensions compared to carrier diffusion lengths (allowing charge collection), and the larger volume of the drain/source silicon leading to increased volume for charge generation to drive the bipolar action.

Figure 6. Drain and source currents for the hit to the drain region (top) and
source (bottom) at three locations. Figures on the right show initial 40 picoseconds.



ATLAS 3D Device simulations are used to simulate the impact of single event charge injection into a sub-50nm FinFET device. Simulation results indicated that the injected charge is amplified by transient transistor action, and that the sensitive areas of such devices may include source and drain regions.



  1. X Huang et. al., "Sub 50-nm FinFET:PMOS", IEDM Technical Digest, 1999.
  2. R. Chau et. al., Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate, and Tri-Gate", 2002 International Conference on Solid State Devices and Materials (SSDM 2002), Nagoya, Japan.
  3. Linda Geppert, "Triple Gate, Double Play", IEEE Spectrum, November 1, 2002.
  4. G. E. Davis et. al, "Transient Radiation Effects in SOI Memories, IEEE Transactions on Nuclear Science, vol. NS-32, pp. 4432-4437, December 1985.
  5. M. Alles, "SPICE Analysis of the SEU Sensitivity of a Fully Depleted SOI CMOS SRAM Cell, IEEE Transactions of Nuclear Science, vol. NS-41, pp. 2093-2097, December 1994.
  6. J.-P. Colinge ed., Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, pp. 169, 1991.
  7. J. Kedzierski et al., "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation", IEDM Technical Digest, pp. 247-250, December 2002.
  8. Y.-K. Choi et al., "FinFET Process Refinements for Improved Mobility and Gate Function Engineering", IEDM Technical Digest, pp. 259-262, December 2002.
  9. ATLAS Users Manual, Volume II, Silvaco International, 2001.
    [10] P. Dodd et. al., "SEU-Sensitive Volumes in Bulk and SOI SRAMs From First-Principles Calculations and Experiments", IEEE Transactions of Nuclear Science, pp. 1893-1903, December 2001.

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